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Searched refs:idx (Results 1 – 25 of 89) sorted by relevance

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/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/mcdi/
A Dmt_lp_irqremain.c68 uint32_t idx; in mt_lp_irqremain_init() local
73 idx = remain_irqs.count; in mt_lp_irqremain_init()
80 idx = remain_irqs.count; in mt_lp_irqremain_init()
87 idx = remain_irqs.count; in mt_lp_irqremain_init()
94 idx = remain_irqs.count; in mt_lp_irqremain_init()
101 idx = remain_irqs.count; in mt_lp_irqremain_init()
108 idx = remain_irqs.count; in mt_lp_irqremain_init()
115 idx = remain_irqs.count; in mt_lp_irqremain_init()
122 idx = remain_irqs.count; in mt_lp_irqremain_init()
129 idx = remain_irqs.count; in mt_lp_irqremain_init()
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/
A Dimx8m_csu.c19 val = mmio_read_32(CSLx_REG(csu->idx)); in imx_csu_init()
20 if (val & CSLx_LOCK(csu->idx)) { in imx_csu_init()
23 mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx), in imx_csu_init()
27 val = mmio_read_32(CSU_HP_REG(csu->idx)); in imx_csu_init()
28 if (val & CSU_HP_LOCK(csu->idx)) { in imx_csu_init()
31 mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx), in imx_csu_init()
35 val = mmio_read_32(CSU_SA_REG(csu->idx)); in imx_csu_init()
36 if (val & CSU_SA_LOCK(csu->idx)) { in imx_csu_init()
39 mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx), in imx_csu_init()
44 if (val & CSU_HPCONTROL_LOCK(csu->idx)) { in imx_csu_init()
[all …]
/arm-trusted-firmware-2.8.0/lib/extensions/amu/
A Damu_private.h23 uint64_t amu_group0_cnt_read_internal(unsigned int idx);
24 void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
26 uint64_t amu_group1_cnt_read_internal(unsigned int idx);
27 void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
28 void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val);
31 uint64_t amu_group0_voffset_read_internal(unsigned int idx);
32 void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val);
34 uint64_t amu_group1_voffset_read_internal(unsigned int idx);
35 void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val);
/arm-trusted-firmware-2.8.0/drivers/st/ddr/
A Dstm32mp_ram.c46 uint32_t idx; in stm32mp_ddr_dt_get_param() local
48 for (idx = 0U; idx < param_size; idx++) { in stm32mp_ddr_dt_get_param()
49 ret = fdt_read_uint32_array(fdt, node, param[idx].name, param[idx].size, in stm32mp_ddr_dt_get_param()
50 (void *)(config + param[idx].offset)); in stm32mp_ddr_dt_get_param()
52 VERBOSE("%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); in stm32mp_ddr_dt_get_param()
54 ERROR("%s: Cannot read %s, error=%d\n", __func__, param[idx].name, ret); in stm32mp_ddr_dt_get_param()
/arm-trusted-firmware-2.8.0/bl31/
A Dehf.c34 #define PRI_BIT(idx) (((ehf_pri_bits_t) 1u) << (idx)) argument
40 #define IDX_TO_PRI(idx) \ argument
44 #define IS_IDX_VALID(idx) \ argument
56 unsigned int idx; in pri_to_idx() local
60 assert(IS_IDX_VALID(idx)); in pri_to_idx()
62 return idx; in pri_to_idx()
123 idx = pri_to_idx(priority); in ehf_activate_priority()
430 idx = pri_to_idx(pri); in ehf_el3_interrupt_handler()
439 IDX_TO_PRI(idx)); in ehf_el3_interrupt_handler()
503 unsigned int idx; in ehf_register_priority_handler() local
[all …]
/arm-trusted-firmware-2.8.0/plat/marvell/armada/common/
A Dmarvell_gicv2.c35 #define A7K8K_ODMI_PMU_IRQ(idx) ((2 + idx) << 12) argument
37 #define A7K8K_ODMI_PMU_GIC_IRQ(idx) (130 + idx) argument
79 unsigned int idx = plat_my_core_pos(); in a7k8k_pmu_interrupt_handler() local
98 mmio_write_32(A7K8K_ODMIN_SET_REG, A7K8K_ODMI_PMU_IRQ(idx)); in a7k8k_pmu_interrupt_handler()
107 unsigned int idx; in mvebu_pmu_interrupt_enable() local
117 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) in mvebu_pmu_interrupt_enable()
118 gicv2_interrupt_set_cfg(A7K8K_ODMI_PMU_GIC_IRQ(idx), in mvebu_pmu_interrupt_enable()
/arm-trusted-firmware-2.8.0/lib/gpt_rme/
A Dgpt_rme.c177 for (idx = 0U; idx < pas_region_cnt; idx++) { in gpt_validate_pas_mappings()
186 if (((pas_regions[idx].base_pa + pas_regions[idx].size) > in gpt_validate_pas_mappings()
204 i, idx); in gpt_validate_pas_mappings()
229 idx, i); in gpt_validate_pas_mappings()
240 idx); in gpt_validate_pas_mappings()
254 idx); in gpt_validate_pas_mappings()
445 for (; idx < end_idx; idx++) { in gpt_generate_l0_blk_desc()
448 idx, &l0_gpt_arr[idx], in gpt_generate_l0_blk_desc()
658 for (idx = 1; idx < pas_count; idx++) { in flush_l0_for_pas_array()
872 for (unsigned int idx = 0U; idx < pas_count; idx++) { in gpt_init_pas_l1_tables() local
[all …]
/arm-trusted-firmware-2.8.0/include/lib/extensions/
A Dras_arch.h200 return mmio_read_64(base + ERR_FR(idx)); in ser_get_feature()
205 return mmio_read_64(base + ERR_CTLR(idx)); in ser_get_control()
210 return mmio_read_64(base + ERR_STATUS(idx)); in ser_get_status()
224 static inline void ser_set_status(uintptr_t base, unsigned int idx, in ser_set_status() argument
227 mmio_write_64(base + ERR_STATUS(idx), status); in ser_set_status()
232 return mmio_read_64(base + ERR_ADDR(idx)); in ser_get_addr()
237 return mmio_read_64(base + ERR_MISC0(idx)); in ser_get_misc0()
242 return mmio_read_64(base + ERR_MISC1(idx)); in ser_get_misc1()
249 static inline void ser_sys_select_record(unsigned int idx) in ser_sys_select_record() argument
254 assert(idx < max_idx); in ser_sys_select_record()
[all …]
/arm-trusted-firmware-2.8.0/drivers/arm/rss/
A Drss_comms.c83 size_t idx; in psa_call() local
105 for (idx = 0; idx < in_len; idx++) { in psa_call()
106 VERBOSE("in_vec[%lu].len=%lu\n", idx, in_vec[idx].len); in psa_call()
107 VERBOSE("in_vec[%lu].buf=%p\n", idx, (void *)in_vec[idx].base); in psa_call()
140 for (idx = 0U; idx < out_len; idx++) { in psa_call()
141 VERBOSE("out_vec[%lu].len=%lu\n", idx, out_vec[idx].len); in psa_call()
142 VERBOSE("out_vec[%lu].buf=%p\n", idx, (void *)out_vec[idx].base); in psa_call()
/arm-trusted-firmware-2.8.0/tools/cert_create/src/
A Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/arm-trusted-firmware-2.8.0/tools/encrypt_fw/src/
A Dcmd_opt.c43 const char *cmd_opt_get_name(int idx) in cmd_opt_get_name() argument
45 if (idx >= num_reg_opt) { in cmd_opt_get_name()
49 return long_opt[idx].name; in cmd_opt_get_name()
52 const char *cmd_opt_get_help_msg(int idx) in cmd_opt_get_help_msg() argument
54 if (idx >= num_reg_opt) { in cmd_opt_get_help_msg()
58 return help_msg[idx]; in cmd_opt_get_help_msg()
/arm-trusted-firmware-2.8.0/lib/extensions/amu/aarch64/
A Damu.c331 assert(idx < read_amcgcr_el0_cg0nc()); in amu_group0_cnt_read()
340 assert(idx < read_amcgcr_el0_cg0nc()); in amu_group0_cnt_write()
354 switch (idx) { in amu_group0_voffset_supported()
380 assert(idx < read_amcgcr_el0_cg0nc()); in amu_group0_voffset_read()
381 assert(idx != 1U); in amu_group0_voffset_read()
395 assert(idx < read_amcgcr_el0_cg0nc()); in amu_group0_voffset_write()
396 assert(idx != 1U); in amu_group0_voffset_write()
408 assert(idx < read_amcgcr_el0_cg1nc()); in amu_group1_cnt_read()
418 assert(idx < read_amcgcr_el0_cg1nc()); in amu_group1_cnt_write()
433 assert(idx < read_amcgcr_el0_cg1nc()); in amu_group1_voffset_read()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/
A Dmt_spm_pmic_wrap.c113 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
125 for (idx = 0; idx < pw->set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
127 data = pw->set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
128 mmio_write_32(pw->addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
143 if (pw == NULL || idx >= pw->set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
147 pw->set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
151 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
152 mmio_write_32(pw->addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
161 (pw != NULL && idx < pw->set[phase].nr_idx)) { in mt_spm_pmic_wrap_get_cmd()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_pmic_wrap.c102 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
144 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/mcdi/
A Dmt_lp_irqremain.c57 uint32_t idx; in mt_lp_irqremain_init() local
62 idx = remain_irqs.count; in mt_lp_irqremain_init()
63 remain_irqs.irqs[idx] = KEYPAD_IRQ_ID; in mt_lp_irqremain_init()
64 remain_irqs.wakeupsrc_cat[idx] = 0; in mt_lp_irqremain_init()
65 remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC; in mt_lp_irqremain_init()
/arm-trusted-firmware-2.8.0/plat/mediatek/common/lpm/
A Dmt_lp_rm.c39 int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid) in mt_lp_rm_reset_constraint() argument
43 if ((plat_mt_rm.plat_rm == NULL) || (idx < 0) || in mt_lp_rm_reset_constraint()
44 (idx >= plat_mt_rm.count)) { in mt_lp_rm_reset_constraint()
48 rc = plat_mt_rm.plat_rm->consts[idx]; in mt_lp_rm_reset_constraint()
57 int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid, in mt_lp_rm_find_and_run_constraint() argument
64 if ((rm == NULL) || (idx < 0) || (idx >= plat_mt_rm.count)) { in mt_lp_rm_find_and_run_constraint()
76 for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) { in mt_lp_rm_find_and_run_constraint()
/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/src/
A Diommu.c316 ARM_SMMU_GR0_SMR(idx)), reg); in arm_smmu_smr_cfg()
329 ARM_SMMU_GR0_S2CR(idx)), reg); in arm_smmu_s2cr_cfg()
404 uint32_t idx; in arm_smmu_create_identity_map() local
441 for (idx = 0; idx < smmu->streams; idx++) { in arm_smmu_create_identity_map()
448 arm_smmu_s2cr_cfg(smmu, idx); in arm_smmu_create_identity_map()
451 smmu->smr[idx].mask = smmu->stream_ids_mask[idx]; in arm_smmu_create_identity_map()
452 smmu->smr[idx].id = smmu->stream_ids[idx]; in arm_smmu_create_identity_map()
453 smmu->smr[idx].valid = 1; in arm_smmu_create_identity_map()
454 arm_smmu_smr_cfg(smmu, idx); in arm_smmu_create_identity_map()
461 reg = smmu->cfg[idx].cbar; in arm_smmu_create_identity_map()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spm/
A Dspm_pmic_wrap.c117 uint32_t idx, addr, data; in mt_spm_pmic_wrap_set_phase() local
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
147 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
150 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
156 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
165 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_get_cmd()
[all …]
/arm-trusted-firmware-2.8.0/lib/fconf/
A Dfconf_amu_getter.c38 uintptr_t idx = 0U; in fconf_populate_amu_cpu_amu() local
45 ret = fdt_get_reg_props_by_index(fdt, node, 0, &idx, NULL); in fconf_populate_amu_cpu_amu()
56 amu->enable |= (1 << idx); in fconf_populate_amu_cpu_amu()
76 int idx; in fconf_populate_amu_cpu() local
95 idx = plat_core_pos_by_mpidr(mpidr); in fconf_populate_amu_cpu()
96 if (idx < 0) { in fconf_populate_amu_cpu()
100 amu = &fconf_amu_topology_.cores[idx]; in fconf_populate_amu_cpu()
/arm-trusted-firmware-2.8.0/drivers/auth/
A Dimg_parser_mod.c69 unsigned int idx; in img_parser_check_integrity() local
80 idx = parser_lib_indices[img_type]; in img_parser_check_integrity()
81 assert(idx != INVALID_IDX); in img_parser_check_integrity()
84 return parser_lib_descs[idx].check_integrity(img_ptr, img_len); in img_parser_check_integrity()
103 unsigned int idx; in img_parser_get_auth_param() local
120 idx = parser_lib_indices[img_type]; in img_parser_get_auth_param()
121 assert(idx != INVALID_IDX); in img_parser_get_auth_param()
124 return parser_lib_descs[idx].get_auth_param(type_desc, img_ptr, img_len, in img_parser_get_auth_param()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/mcdi/
A Dmt_lp_irqremain.c62 uint32_t idx; in mt_lp_irqremain_init() local
67 idx = remain_irqs.count; in mt_lp_irqremain_init()
68 remain_irqs.irqs[idx] = KEYPAD_IRQ_ID; in mt_lp_irqremain_init()
69 remain_irqs.wakeupsrc_cat[idx] = 0U; in mt_lp_irqremain_init()
70 remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC; in mt_lp_irqremain_init()
/arm-trusted-firmware-2.8.0/drivers/st/clk/
A Dclk-stm32-core.h225 [(idx)] = (struct clk_stm32){ \
240 [(idx)] = (struct clk_stm32){ \
259 [(idx)] = (struct clk_stm32){ \
270 [(idx)] = (struct clk_stm32){ \
282 [(idx)] = (struct clk_stm32){ \
296 [(idx)] = (struct clk_stm32){ \
311 #define CLK_FIXED_RATE(idx, _binding, _rate) \ argument
312 [(idx)] = (struct clk_stm32){ \
361 #define CLK_OSC(idx, _idx, _parent, _osc_id) \ argument
362 [(idx)] = (struct clk_stm32){ \
[all …]
/arm-trusted-firmware-2.8.0/drivers/st/iwdg/
A Dstm32_iwdg.c91 uint32_t idx; in stm32_iwdg_init() local
95 idx = stm32_iwdg_get_instance(dt_info.base); in stm32_iwdg_init()
96 iwdg = &stm32_iwdg[idx]; in stm32_iwdg_init()
112 hw_init = stm32_iwdg_get_otp_config(idx); in stm32_iwdg_init()
117 idx + 1U); in stm32_iwdg_init()
137 VERBOSE("IWDG%u found, %ssecure\n", idx + 1U, in stm32_iwdg_init()
148 if (stm32_iwdg_shadow_update(idx, iwdg->flags) != BSEC_OK) { in stm32_iwdg_init()
/arm-trusted-firmware-2.8.0/services/std_svc/sdei/
A Dsdei_event.c27 long int idx; in get_event_entry() local
35 idx = MAP_OFF(map, mapping); in get_event_entry()
45 return &cpu_priv_base[idx]; in get_event_entry()
48 idx = MAP_OFF(map, mapping); in get_event_entry()
50 return &sdei_shared_event_table[idx]; in get_event_entry()

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