| /arm-trusted-firmware-2.8.0/lib/zlib/ |
| A D | inffast.c | 82 in = strm->next_in;
83 last = in + (strm->avail_in - 5);
105 hold += (unsigned long)(*in++) << bits;
107 hold += (unsigned long)(*in++) << bits;
127 hold += (unsigned long)(*in++) << bits;
136 hold += (unsigned long)(*in++) << bits;
138 hold += (unsigned long)(*in++) << bits;
290 } while (in < last && out < end);
294 in -= len;
299 strm->next_in = in;
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| /arm-trusted-firmware-2.8.0/docs/perf/ |
| A D | psci-performance-juno.rst | 5 operations in the Trusted Firmware-A Power State Coordination Interface (PSCI)
43 console output prevented some of the tests from executing in parallel.
50 then initiates the test on all CPUs in parallel.
52 - **Sequential Tests** This type of test powers on each non-lead CPU in
85 ``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
117 ``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
137 variance in ``PSCI_ENTRY`` times across CPUs is due to lock contention in Juno
152 ``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
184 ``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
208 for the CPUs in little cluster due to greater CPU performance.
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | rpi3.rst | 30 the cores boot in AArch64 mode.
35 SD card, it will load it and execute in EL2 in AArch64. Basically, it executes
39 **0x0** (instead of the default stub) and execute it in EL3 in AArch64. All
54 in AArch32. This means that BL33 can't be in EL2 in AArch64 mode. The
152 level. If BL33 was running in EL2 in AArch64 (as in the default bootflow of
153 TF-A) it could only jump to the kernel in AArch32 in Supervisor mode.
198 ones in the memory map. The resulting file is ``armstub8.bin``, located in the
206 in AArch64 mode. If set to 1, it will jump to BL33 in Hypervisor in AArch32
227 DTB in memory.
284 able to set ROT_KEY to your own key in PEM format. Also in order to build,
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| A D | hikey960.rst | 6 More information are listed in `link`_.
33 Make all the repositories in the same ${BUILD\_PATH}.
43 - Create the symbol link to OpenPlatformPkg in edk2.
68 *Make sure that you're using the sgdisk in the l-loader directory.*
83 that fails to display in minicom.
95 Append one line for serial-over-USB in *#ser2net.conf*
116 Boot UEFI in recovery mode
119 - Fetch that are used in recovery mode. The code location is in below.
153 - UEFI running in recovery mode.
170 - Notice: UEFI could also boot kernel in recovery mode, but BL31 isn't loaded in
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| A D | rpi4.rst | 5 Arm Cortex-A72 cores. Also in contrast to previous Raspberry Pi versions this
29 ``config.txt``. You should have AArch64 code in the file loaded as the
33 Other options that should be set in ``config.txt`` to properly boot 64-bit
42 The BL31 code will patch the provided device tree blob in memory to advertise
55 port, also it deviates quite a lot from the RPi3 port in many other ways.
57 two could be (more) unified in the future.
70 load this file to the beginning of DRAM (address 0) and execute it in
74 setting them in ``config.txt``. If the GPU firmware finds a magic value in the
75 armstub image file, it will put those two load addresses in memory locations
79 entry point, also put the DTB address in the x0 register, as requested by
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/ |
| A D | arm-build-options.rst | 7 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
8 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
9 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
23 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
48 in which case the platform is configured to expect NULL in the State-ID
98 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
104 SP nodes in tb_fw_config.
111 internal-trusted-storage) as SP in tb_fw_config device tree.
119 |FIP in a GPT image|
122 map is explained in the :ref:`Firmware Design`.
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-1.rst | 5 | Title | Malformed Firmware Update SMC can result in copy of |
30 functionality in BL1. When cold boot reaches the EL3 Runtime Software (for
43 the cold boot path, before BL31 starts. Untrusted in this sense means code
44 that is not in ROM or has not been authenticated or has otherwise been
50 The vulnerabilities consist of potential integer overflows in the input
58 Two of the vulnerabilities are in the function ``bl1_fwu_image_copy()`` in
84 INFO("BL1-FWU: Continuing image copy in blocks\n");
98 result in an unexpectedly large copy of data into secure memory.
128 large value of ``image_size`` may result in an integer overflow in the 2nd
137 - Line 88 of ``plat/arm/common/arm_bl1_fwu.c`` in function of
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| A D | security-advisory-tfv-4.rst | 5 | Title | Malformed Firmware Update SMC can result in copy or |
6 | | authentication of unexpected data in secure memory in |
19 | Impact | Copy or authentication of unexpected data in the secure |
31 result in a value large enough to wrap around, which may lead to unpredictable
55 then, the ``check_uptr_overflow()`` macro was not used in AArch32 code.
57 The vulnerability resides in the BL1 FWU SMC handling code and it may be
62 - Platform code uses the Firmware Update (FWU) code provided in
68 overflows in the input validation checks while handling the
90 secure memory if the memory is mapped in BL1's address space, or cause a fatal
94 resident in secure memory. This is implemented by the ``bl1_fwu_image_auth()``
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| /arm-trusted-firmware-2.8.0/docs/ |
| A D | requirements.txt | 41 # via -r requirements.in
47 # via -r requirements.in
62 # -r requirements.in
67 # via -r requirements.in
77 # via -r requirements.in
89 # The following packages are considered to be unsafe in a requirements file:
|
| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | alt-boot-flows.rst | 13 configuration required to put the system in the expected state.
30 The system is left in the same state as when entering BL31 in the default boot
33 - Running in EL3;
48 - The EL3 payload may reside in non-volatile memory (NVM) and execute in
50 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
52 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
55 To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
56 used. The infinite loop that it introduces in BL1 stops execution at the right
60 It is expected that this loading method will work in most cases, as a debugger
61 connection is usually available in a pre-production system. The user is free to
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| A D | interrupt-framework-design.rst | 19 level in the normal world when the execution is in secure world at
46 always handled in EL3.
148 in Secure-EL1/Secure-EL0 is in control of how its execution is preempted
158 in EL3 can handle the interrupt.
212 cannot be handled in EL3.
215 in EL3.
249 model in the ``flags`` field to the corresponding bit in the ``SCR_EL3`` for each
292 which runs only in Secure-EL1.
362 is as described in Section 2.
577 #. **CSS=1, TEL3=0**. Non-secure interrupts are handled in the FEL in
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| A D | psci-pd-tree.rst | 9 populate a tree that describes the hierarchy of power domains in the
11 requires a change in the code.
14 in a data structure.
17 tree. It also uses an MPIDR to find a node in the tree. The assumption that
20 levels in the power domain tree to four.
68 #. The value in each entry in the array is used to find the number of entries
121 Removing assumptions about MPIDRs used in a platform
143 relationship allows the core nodes to be allocated in a separate array
145 core in the array is the same as the return value from these APIs.
147 Dealing with holes in MPIDR allocation
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| A D | trusted-board-boot.rst | 11 Arm DEN0006D. It should be used in conjunction with the
47 extension fields in the `X.509 v3`_ certificates.
60 one of the extension fields in the trusted world certificate.
66 extension fields in the trusted world certificate.
72 in one of the extension fields in the corresponding key certificate.
74 The following images are included in the CoT:
192 enabled through use of specific build flags as described in
198 Authentication module included in TF-A.
201 described in the following sections.
208 implement the boot requirements specified in the
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| A D | reset-design.rst | 5 resets in Trusted Firmware-A (TF-A). It also describes how the platform
7 resulting in a simplified and more optimised boot flow.
9 This document should be used in conjunction with the :ref:`Firmware Design`
16 The TF-A reset code is implemented in BL1 by default. The following high-level
28 above is still relevant, as all these operations will occur in BL31 in
40 If the reset vector address (reflected in the reset vector base address register
43 detection can be skipped, resulting in the following boot flow:
65 applies. This results in the following boot flow:
82 This results in the following boot flow:
101 logic in the BL31 entry point to support this use case.
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| A D | auth-framework.rst | 181 described in this document).
198 by the PP in the CoT.
211 in the CoT described in Diagram 2, each certificate can be loaded and
278 The platform may specify these methods in the CoT in case it decides to define
567 (child) in a CoT.
576 Describing an image in a CoT
583 to locate the image in a FIP and load it in the memory reserved for the data
584 image in the CoT.
878 parameter in the signature authentication method. The key is stored in the
925 in this file.
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | romlib-design.rst | 4 This document provides an overview of the "library at ROM" implementation in
11 be placed in ROM. This reduces SRAM usage by utilising the available space in
13 are placed in ROM. The capabilities of the "library at ROM" are:
19 3. Platform-specific libraries can be placed in ROM.
30 placed in ROM. The index file is platform specific and its format is:
37 function -- Name of the function to be placed in library at ROM
40 It is also possible to insert reserved spaces in the list by using the keyword
47 The reserved spaces can be used to add more functions in the future without
48 affecting the order and location of functions already existing in the jump
94 used in makefiles.
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| A D | secure-partition-manager-mm.rst | 30 in the system, i.e. EL3 in Trusted Firmware-A (TF-A). The service requirements are
67 services in EL3 and instantiate the rest in a partition in S-EL0.
143 `instructions in the EDK2 repository`_.
146 image in the FIP:
239 In order to instantiate one or more secure services in the Secure Partition in
403 architectural setup to enable execution in S-EL0
471 "Return State" column of Table 3-1 in Section 3.1 "Register use in AArch64 SMC
494 - ``X1``: Size of the buffer in bytes.
533 code in response to a runtime event.
687 memory region the Base Address lies in.
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| /arm-trusted-firmware-2.8.0/ |
| A D | dco.txt | 17 (a) The contribution was created in whole or in part by me and I
19 indicated in the file; or
24 work with modifications, whether created in whole or in part
27 in the file; or
|
| /arm-trusted-firmware-2.8.0/lib/compiler-rt/ |
| A D | LICENSE.TXT | 17 Copyright (c) 2009-2016 by the contributors listed in CREDITS.TXT
39 * Redistributions in binary form must reproduce the above copyright notice,
40 this list of conditions and the following disclaimers in the
58 Copyright (c) 2009-2015 by the contributors listed in CREDITS.TXT
62 in the Software without restriction, including without limitation the rights
67 The above copyright notice and this permission notice shall be included in
82 have its own individual LICENSE.TXT file in the directory in which it appears.
86 The disclaimer of warranty in the University of Illinois Open Source License
87 applies to all code in the LLVM Distribution, and nothing in any of the
|
| /arm-trusted-firmware-2.8.0/plat/arm/board/common/swd_rotpk/ |
| A D | README | 2 root-of-trust key used in the CCA chain of trust.
4 * swd_rotprivk_rsa.pem is a 2K RSA private key in PEM format. It has been
13 openssl rsa -in arm_swd_rotprivk_rsa.pem -pubout -outform DER | \
|
| /arm-trusted-firmware-2.8.0/docs/plat/arm/juno/ |
| A D | index.rst | 21 binaries in the ``SOFTWARE/`` directory with custom built TF-A binaries.
48 For the FVP, the kernel FDT is packaged in FIP during build and loaded
67 package included in the Linaro release:
123 - Build BL32 in AArch32.
153 The resulting BL1 and FIP images may be found in:
171 The new images must be programmed in flash memory by adding
172 an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
176 overlap with any other entries in the file.
200 If the EL3 payload is able to execute in place, it may be programmed in flash
209 For more information on EL3 payloads in general, see
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| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | security.rst | 13 issues in the project's `issue tracker`_ with the ``security-advisory`` tag. You
25 report it in the `issue tracker`_ or on the `mailing list`_. Instead, please
31 outlined in the process. We do our best to respond and fix any issues quickly.
39 We will name and thank you in the :ref:`Change Log & Release Notes` distributed
40 with the source code and in any published security advisory.
48 | |TFV-1| | Malformed Firmware Update SMC can result in copy of unexpectedly |
56 | |TFV-4| | Malformed Firmware Update SMC can result in copy or |
57 | | authentication of unexpected data in secure memory in AArch32 |
|
| A D | coding-guidelines.rst | 14 rules set out in this file can be automatically applied when you are editing
15 files in the |TF-A| repository.
29 source tree. The project also defines certain *checkpatch* options in the
30 ``.checkpatch.conf`` file in the top-level directory.
230 This is in contrast to code in a Linux environment, which is less tightly
258 always take action, even in release builds.
333 the system from executing in this state indefinitely.
344 Use of built-in *C* and *libc* data types
354 data stored, which the built-in *C* types guarantee.
417 code in case of error. This practice should be used sparingly.
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| /arm-trusted-firmware-2.8.0/plat/allwinner/common/ |
| A D | arisc_off.S | 12 # The encoded instructions go into an array defined in
17 # start address in the reset vector), to be actually triggered by that
19 # It expects the core number presented as a mask in the upper half of
20 # r3, so to be patched in the lower 16 bits of the first instruction,
21 # overwriting the 0 in this code here.
25 # - Loop until the core in question reaches WFI.
27 # respective core bit in CPUX_PWROFF_GATING_REG (0x1f01500).
78 l.j reset # just in case ....
89 l.sfeq r5, r0 # is it not yet in WFI?
|
| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | porting-guide.rst | 124 levels in the platform.
597 registers in case of an unhandled exception in BL31. This aids in debugging
620 specific address in the BL31 image in the same processor mode as it was
767 cookie in the first argument may be used to select the counter in case the
832 hash is saved in OTP.
1042 This function plays a crucial role in the power domain topology framework in
1075 A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
1340 never returns. Failure in reset results in panic.
2296 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2324 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
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