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/arm-trusted-firmware-2.8.0/fdts/
A Dstm32mp151.dtsi34 #interrupt-cells = <3>;
35 interrupt-controller;
76 interrupt-parent = <&intc>;
239 interrupt-controller;
240 #interrupt-cells = <3>;
245 interrupt-controller;
246 #interrupt-cells = <2>;
254 interrupt-controller;
548 interrupt-controller;
559 interrupt-controller;
[all …]
A Dfvp-ve-Cortex-A7x1.dts7 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
50 gic: interrupt-controller@2c001000 {
52 #interrupt-cells = <3>;
54 interrupt-controller;
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 63>;
82 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
A Dcorstone700.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
34 gic: interrupt-controller@1c000000 {
36 #interrupt-cells = <3>;
38 interrupt-controller;
76 interrupt-parent = <&gic>;
85 interrupt-parent = <&gic>;
120 interrupt-names = "mhu_rx";
132 interrupt-names = "mhu_rx";
144 interrupt-names = "mhu_rx";
A Dstm32mp131.dtsi63 #interrupt-cells = <3>;
64 interrupt-controller;
78 interrupt-parent = <&intc>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
478 interrupt-controller;
490 interrupt-controller;
502 interrupt-controller;
514 interrupt-controller;
526 interrupt-controller;
[all …]
A Dn1sdp.dtsi6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
90 gic: interrupt-controller@30000000 {
93 #interrupt-cells = <3>;
96 interrupt-controller;
137 interrupt-names = "eventq", "cmdq-sync", "gerror";
149 interrupt-names = "eventq", "cmdq-sync", "gerror";
167 #interrupt-cells = <1>;
168 interrupt-map-mask = <0 0 0 7>;
190 #interrupt-cells = <1>;
[all …]
A Dfvp-base-gicv2.dtsi10 gic: interrupt-controller@2f000000 {
12 #interrupt-cells = <3>;
14 interrupt-controller;
A Dmorello.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
20 gic: interrupt-controller@2c010000 {
23 #interrupt-cells = <3>;
26 interrupt-controller;
57 interrupt-names = "mhu_lpri_rx",
A Dfvp-base-gicv3.dtsi10 gic: interrupt-controller@2f000000 {
12 #interrupt-cells = <3>;
16 interrupt-controller;
A Dfvp-ve-Cortex-A5x1.dts7 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
70 gic: interrupt-controller@2c001000 {
72 #interrupt-cells = <3>;
74 interrupt-controller;
145 #interrupt-cells = <1>;
146 interrupt-map-mask = <0 0 63>;
147 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
A Da5ds.dts12 interrupt-parent = <&gic>;
97 gic: interrupt-controller@1c001000 {
99 #interrupt-cells = <3>;
101 interrupt-controller;
110 interrupt-parent = <&gic>;
119 interrupt-parent = <&gic>;
150 interrupt-parent = <&gic>;
A Dmorello-soc.dts81 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
99 #interrupt-cells = <1>;
100 interrupt-map-mask = <0 0 0 7>;
101 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
117 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
135 #interrupt-cells = <1>;
136 interrupt-map-mask = <0 0 0 7>;
137 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
152 interrupt-names = "eventq", "gerror", "cmdq-sync";
162 interrupt-names = "DPU";
A Dcorstone700_fpga.dts18 interrupt-parent = <&gic>;
27 interrupt-parent = <&gic>;
A Darm_fpga.dts11 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
89 gic: interrupt-controller@30000000 {
92 #interrupt-cells = <3>;
95 interrupt-controller;
A Dfvp-foundation-gicv2-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 interrupt-parent = <&gic>;
90 gic: interrupt-controller@2f000000 {
92 #interrupt-cells = <3>;
94 interrupt-controller;
A Dfvp-foundation-gicv3-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 interrupt-parent = <&gic>;
90 gic: interrupt-controller@2f000000 {
92 #interrupt-cells = <3>;
96 interrupt-controller;
A Dfvp-base-psci-common.dtsi13 #include <dt-bindings/interrupt-controller/arm-gic.h>
26 interrupt-parent = <&gic>;
81 * terminology. Each interrupt property descriptor has 3 fields:
84 * 3. Type of interrupt (Edge or Level configured)
205 #interrupt-cells = <1>;
206 interrupt-map-mask = <0 0 63>;
207 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
A Dn1sdp-multi-chip.dts63 interrupt-names = "eventq", "cmdq-sync", "gerror";
81 #interrupt-cells = <1>;
82 interrupt-map-mask = <0 0 0 7>;
83 interrupt-map = <0 0 0 1 &gic 0 0 0 649 IRQ_TYPE_LEVEL_HIGH>,
/arm-trusted-firmware-2.8.0/docs/components/
A Dplatform-interrupt-controller-API.rst22 is read to determine the priority of the interrupt.
76 interrupt.
136 returns ``1`` for all interrupt types.
142 - For interrupt type ``INTR_TYPE_EL3``:
150 - For interrupt type ``INTR_TYPE_S_EL1``:
179 assign the interrupt to the right group.
183 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
185 - ``INTR_TYPE_S_EL1`` maps to Secure Group 1 interrupt.
187 - ``INTR_TYPE_EL3`` maps to Secure Group 0 interrupt.
191 - ``INTR_TYPE_NS`` maps to Group 1 interrupt.
[all …]
A Dexception-handling.rst112 handling concludes by EOIing the interrupt.
171 Dispatchers are assigned interrupt priority levels in two steps:
272 The interrupt handler should have the following signature:
409 deactivating interrupt:
480 #. A Non-secure interrupt preempts Secure execution. Non-secure interrupt is
519 interrupt handler.
540 interrupt, and is taken to EL3.
547 the interrupt received.
556 .. _non-interrupt-flow:
559 interrupt:
[all …]
A Dsecure-partition-manager.rst1106 trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt
1119 Non-secure interrupt handling
1126 - Non-secure interrupt is signaled.
1128 - Non-secure interrupt is queued.
1136 Secure interrupt handling
1163 Secure interrupt signaling mechanisms
1195 Secure interrupt completion mechanisms
1210 deactivation of the secure virtual interrupt.
1242 The following figure describes interrupt handling flow when a secure interrupt
1258 interrupt is not masked i.e., PSTATE.I = 0
[all …]
/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_pm.c32 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; in stm32_cpu_standby() local
42 while (interrupt == GIC_SPURIOUS_INTERRUPT) { in stm32_cpu_standby()
46 interrupt = gicv2_acknowledge_interrupt(); in stm32_cpu_standby()
48 if ((interrupt != PENDING_G1_INTID) && in stm32_cpu_standby()
49 (interrupt != GIC_SPURIOUS_INTERRUPT)) { in stm32_cpu_standby()
50 gicv2_end_of_interrupt(interrupt); in stm32_cpu_standby()
/arm-trusted-firmware-2.8.0/docs/design/
A Dinterrupt-framework-design.rst35 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
39 #. Non-secure interrupt. This type of interrupt can be routed to EL3,
44 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
149 by EL3 interrupt and can handover the interrupt to EL3 for handling.
189 interrupt signal, and if any one of the interrupt type sets **TEL3=1** for a
208 and Secure-EL1 interrupt), only interrupt controller architectures
352 the type of interrupt.
631 When an interrupt is generated, the vector for each interrupt type is
693 #. Validating the interrupt. This involves ensuring that the interrupt was
697 the interrupt was taken from to determine this. If the interrupt is not
[all …]
A Dindex.rst12 interrupt-framework-design
/arm-trusted-firmware-2.8.0/docs/resources/diagrams/plantuml/
A Dsdei_general.puml12 participant "SDEI interrupt source" as SDEI
26 SDEI-->EL3: SDEI interrupt
/arm-trusted-firmware-2.8.0/lib/extensions/ras/
A Dras_common.c74 .interrupt = 0, in ras_ea_handler()
133 .interrupt = intr_raw, in ras_interrupt_handler()

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