Searched refs:interval (Results 1 – 11 of 11) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046ardb/ |
| A D | ddr_init.c | 54 .interval = U(0x1FFE07FF),
99 .interval = U(0x1B6C06DB),
147 .interval = U(0x18600618),
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160aqds/ |
| A D | ddr_init.c | 63 .interval = U(0x30C00000),
114 .interval = U(0x2C2E0000),
165 .interval = U(0x279C0000),
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2162aqds/ |
| A D | ddr_init.c | 63 .interval = U(0x30C00000),
114 .interval = U(0x2C2E0000),
165 .interval = U(0x279C0000),
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| /arm-trusted-firmware-2.8.0/include/drivers/nxp/ddr/ |
| A D | ddr.h | 60 unsigned int interval; member
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ls1043ardb/ |
| A D | ddr_init.c | 42 .interval = U(0x18600618),
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046afrwy/ |
| A D | ddr_init.c | 43 .interval = U(0x18600618),
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ls1028ardb/ |
| A D | ddr_init.c | 40 .interval = U(0x18600618),
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| /arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/ |
| A D | ddrc.c | 262 regs->interval & ~SDRAM_INTERVAL_BSTOPRE); in ddrc_set_regs()
264 ddr_out32(&ddr->sdram_interval, regs->interval); in ddrc_set_regs()
542 ddr_out32(&ddr->sdram_interval, regs->interval); in ddrc_set_regs()
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| A D | regs.c | 517 regs->interval = ((refint & 0xFFFF) << 16) | in cal_ddr_sdram_interval()
519 debug("interval = 0x%x\n", regs->interval); in cal_ddr_sdram_interval()
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160ardb/ |
| A D | ddr_init.c | 43 .interval = U(0x18600000),
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | rz-g2.rst | 185 NOTICE: BL2: DRAM refresh interval 1.95 usec
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