| /arm-trusted-firmware-2.8.0/drivers/st/regulator/ |
| A D | regulator_core.c | 293 assert(levels != NULL); in regulator_list_voltages()
318 while ((n > 1U) && ((*levels)[n - 1U] > rdev->max_mv)) { in regulator_list_voltages()
323 if (rdev->max_mv != (*levels)[n - 1]) { in regulator_list_voltages()
329 while ((n > 1U) && ((*levels[0U]) < rdev->min_mv)) { in regulator_list_voltages()
330 (*levels)++; in regulator_list_voltages()
342 if (rdev->min_mv != (*levels)[0U]) { in regulator_list_voltages()
450 const uint16_t *levels; in parse_dt() local
493 ret = regulator_list_voltages(rdev, &levels, &size); in parse_dt()
538 const uint16_t *levels; in regulator_register() local
553 rdev->min_mv = levels[0]; in regulator_register()
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| /arm-trusted-firmware-2.8.0/include/drivers/st/ |
| A D | regulator.h | 56 int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count);
82 const uint16_t **levels, size_t *count);
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| A D | stpmic1.h | 184 int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels,
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | exception-handling.rst | 96 dispatchers to one or more priority levels. The dispatchers then register
100 .. __: `Partitioning priority levels`_
135 `Transition of priority levels`_.
171 Dispatchers are assigned interrupt priority levels in two steps:
173 .. _Partitioning priority levels:
175 Partitioning priority levels
240 `Partitioning priority levels`_ section above.
283 example, expects the platform to allocate two different priority levels—
285 same handler to handle both levels.
431 .. __: `Transition of priority levels`_
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| A D | xlat-tables-lib-v2-design.rst | 361 allows up to 4 lookup levels).
372 memory than expected. The reason is that all levels of translation are
379 on the page size, levels 0 and 1 of translation may only allow table
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| A D | ras.rst | 229 priority levels>` for handling RAS exceptions. The platform must then define
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| A D | secure-partition-manager-mm.rst | 259 depending on the implemented Exception levels. In S-EL0, the Supervisor Call
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| A D | secure-partition-manager.rst | 110 SPMC) residing at different exception levels. To permit the FF-A specification
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| /arm-trusted-firmware-2.8.0/drivers/st/pmic/ |
| A D | stpmic1.c | 799 int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels, in stpmic1_regulator_levels_mv() argument
806 *levels = ldo3_special_mode_table; in stpmic1_regulator_levels_mv()
809 *levels = regul->voltage_table; in stpmic1_regulator_levels_mv()
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| A D | stm32mp_pmic.c | 412 const uint16_t **levels, size_t *count) in pmic_list_voltages() argument
416 return stpmic1_regulator_levels_mv(desc->node_name, levels, count); in pmic_list_voltages()
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| /arm-trusted-firmware-2.8.0/docs/perf/ |
| A D | performance-monitoring-unit.rst | 18 The PMU makes 32 counters available at all privilege levels:
50 ``PMCR`` registers. These can be accessed at all privilege levels.
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| A D | psci-performance-juno.rst | 26 levels 0, 1 and 2 respectively. It does not support any retention states.
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| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | security-hardening.rst | 33 levels must defend from those below when the PMU is treated as an attack
71 exception levels) it instructs counters to increment, obtaining event counts
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-7.rst | 78 lower exception levels to temporarily disable the mitigation in their execution
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | psci-pd-tree.rst | 20 levels in the power domain tree to four.
37 domains at higher levels. For example, only a core power domain can be identified
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| A D | firmware-design.rst | 298 functionality from all Exception levels.
841 levels lower than EL3 will request runtime services using the Secure Monitor
1429 levels for that specific CPU. The PSCI service, upon receiving a power down
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| A D | interrupt-framework-design.rst | 20 exception levels lower than EL3. This could be done with or without the
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | porting-guide.rst | 124 levels in the platform.
139 tree at all the power domain levels used by the platform.
1408 correspond to one of the standard log levels defined in debug.h. The platform
1411 increase the number of log levels.
2597 residency statistics. For higher levels (array indices > 0), the residency
2615 residency statistics. For higher levels (array indices > 0), the residency
2630 all its parent power domain levels are also woken up. The generic PSCI code
2737 for the CPU power domain and its parent power domain levels. The handler
2743 for the higher power domain levels depending on the result of state
2767 CPU and its higher parent power domain levels as indicated by the
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| A D | rt-svc-writers-guide.rst | 11 levels lower than EL3 will request runtime services using the Secure Monitor
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| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | threat_model.rst | 139 | | world, including NS-EL0 NS-EL1 and NS-EL2 levels |
142 | | world, including S-EL0 and S-EL1 levels |
227 .. table:: Table 5: Overall risk levels and corresponding aggregate scores
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| /arm-trusted-firmware-2.8.0/docs/ |
| A D | change-log.md | 4956 - Warning levels are now selectable with `W=<1,2,3>`
5506 - Added support to manage both privilege levels in translation regimes that
5507 describe translations for 2 Exception levels, specifically the EL1&0
5883 unexpected traps into the higher exception levels and disable secure
5887 in the higher exception levels.
5899 at multiple power levels.
6477 - Adding the concept of debug log levels.
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