| /arm-trusted-firmware-2.8.0/services/std_svc/sdei/ |
| A D | sdei_event.c | 24 const sdei_mapping_t *mapping; in get_event_entry() local
34 mapping = SDEI_PRIVATE_MAPPING(); in get_event_entry()
35 idx = MAP_OFF(map, mapping); in get_event_entry()
47 mapping = SDEI_SHARED_MAPPING(); in get_event_entry()
48 idx = MAP_OFF(map, mapping); in get_event_entry()
60 const sdei_mapping_t *mapping; in find_event_map_by_intr() local
70 iterate_mapping(mapping, i, map) { in find_event_map_by_intr()
84 const sdei_mapping_t *mapping; in find_event_map() local
93 for_each_mapping_type(i, mapping) { in find_event_map()
94 iterate_mapping(mapping, j, map) { in find_event_map()
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| A D | sdei_main.c | 865 const sdei_mapping_t *mapping; in sdei_shared_reset() local
889 for_each_mapping_type(i, mapping) { in sdei_shared_reset()
890 iterate_mapping(mapping, j, map) { in sdei_shared_reset()
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | imx8m.rst | 83 There is a special case of mapping the DRAM: entire DRAM available on the
86 Mapping the entire DRAM allows the usage of 2MB block mapping in Level-2
88 Level-3 PTE mapping is used instead then additional PTEs would be required,
92 family it should rather be avoided creating additional Level-3 mapping and
93 introduce more PTEs, hence the implementation uses Level-2 mapping which
96 The reason for the MT_RW attribute mapping scheme is the fact that the SMC
102 Therefore, DRAM mapping is done with MT_RW attributes, as it is required for
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| A D | allwinner.rst | 99 The mapping we use on those SoCs is as follows:
131 SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
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| A D | stm32mp1.rst | 67 Memory mapping
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| A D | rpi3.rst | 234 mapping required for an UEFI firmware payload. These changes are needed
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | xlat-tables-lib-v2-design.rst | 19 #. Support for dynamic mapping and unmapping of regions, even while the MMU is
35 support dynamic mapping. ``lib/xlat_mpu``, which configures Arm's MPU
69 - its mapping granularity (optional).
92 contains 512 entries, each mapping 4KB).
109 details can be found in `The memory mapping algorithm`_ section below).
187 The library optionally supports dynamic memory mapping. This feature may be
237 As explained earlier in this document, when the dynamic mapping feature is
356 The memory mapping algorithm
369 The most common reason for needing a sub-table is when a specific mapping
425 mapping cannot be cached in the TLBs.
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| A D | granule-protection-tables-design.rst | 50 mapping is used, or a level 0 entry can link to a level 1 table where relatively
52 step mapping. The type of mapping used for each PAS is determined by the user
98 #. The desired attributes of this memory region (mapping type, PAS type)
111 imply, ``GPT_MAP_REGION_BLOCK`` creates a region using only L0 mapping while
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| A D | secure-partition-manager-mm.rst | 608 address map from a Secure Partition. This is done by mapping these regions in
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| /arm-trusted-firmware-2.8.0/lib/romlib/ |
| A D | romlib_generator.py | 99 def build_template(self, name, mapping=None, remove_comment=False): argument
120 return template.substitute(mapping)
254 mapping = {"jmptbl_address": matching_symbol.group(1)}
257 output_file.write(self.build_template("jmptbl_glob_var.S", mapping))
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| /arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/ |
| A D | dimm.c | 234 if (spd->mapping[i] == udimm_rc_e_dq[i]) { in cal_dimm_params()
238 ptr = (unsigned char *)&spd->mapping[i]; in cal_dimm_params()
391 pdimm->dq_mapping[i] = spd->mapping[i]; in cal_dimm_params()
395 pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0; in cal_dimm_params()
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-3.rst | 31 mapping specifying both ``MT_RO`` and ``MT_EXECUTE_NEVER`` should result in a
49 would only manifest itself for device memory mapped as RO; use of this mapping
50 is considered rare, although the upstream QEMU platform uses this mapping when
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| /arm-trusted-firmware-2.8.0/include/drivers/nxp/ddr/ |
| A D | dimm.h | 93 unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ member
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ |
| A D | soc.def | 79 # Enable dynamic memory mapping
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | stm32mp13-ddr3-1x4Gb-1066-binF.dtsi | 16 * address mapping : RBC
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| A D | stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 13 * Address mapping type: RBC
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| A D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 13 * Address mapping type: RBC
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| A D | stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 15 * address mapping : RBC
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ |
| A D | soc.def | 88 # enable dynamic memory mapping
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ |
| A D | soc.def | 88 # enable dynamic memory mapping
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/ |
| A D | soc.def | 115 # enable dynamic memory mapping
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| /arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/ |
| A D | porting.rst | 26 This file describes the SoC physical memory mapping to be used for the CCU,
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| /arm-trusted-firmware-2.8.0/docs/ |
| A D | change-log.md | 3433 - Refactored header file inclusions and inclusion of memory mapping
3464 - Allow CP1/CP2 mapping at BLE stage
3685 - Added support for mapping the entire LLC into SRAM
4014 - Fixed initialization issues caused by incorrect MPIDR topology mapping
4312 - intel: Modify non secure access function, BL31 address mapping, mailbox's
4408 - arm/fvp: Fix incorrect GIC mapping, BL31 load address and image size for
4550 - qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
4877 - xlat_tables: Support mapping regions without an explicitly specified VA
5598 - Improved memory usage by only mapping TSP memory region when the TSPD has
6022 - Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | interrupt-framework-design.rst | 175 mapping between the type and signal is known only to the platform. The framework
185 Effect of mapping of several interrupt types to one signal
248 The ``scr_el3[2]`` field also stores the routing model but as a mapping of the
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | porting-guide.rst | 54 only for re-mapping peripheral physical addresses and allows platforms with high
56 corresponding to code and data must currently use an identity mapping.
64 an identity mapping for all addresses.
|