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Searched refs:mmio_read_32 (Results 1 – 25 of 463) sorted by relevance

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/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/
A Dhikey_ddr.c24 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
28 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
31 data = mmio_read_32((0xf7800000 + 0x000)); in init_pll()
36 data = mmio_read_32((0xf7800000 + 0x014)); in init_pll()
56 data = mmio_read_32(0xf7032000 + 0x050); in init_pll()
90 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
94 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
99 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
115 data = mmio_read_32((0xf6504000 + 0x054)); in init_freq()
120 data = mmio_read_32((0xf7032000 + 0x104)); in init_freq()
[all …]
A Dhikey_bl_common.c22 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
27 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
30 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
33 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
36 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
39 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
221 data = mmio_read_32(PERI_SC_CLK_SEL0); in init_mmc0_pll()
226 data = mmio_read_32(PERI_SC_CLK_SEL0); in init_mmc0_pll()
285 data = mmio_read_32(PMCTRL_MEDPLLCTRL); in init_media_clk()
309 data = mmio_read_32(PERI_SC_CLK_SEL0); in init_mmc1_pll()
[all …]
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/ddr/
A Dddr_rk3368.c207 fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); in ddr_get_phy_pll_freq()
261 pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
271 pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
277 pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
281 pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
283 pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
301 pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
400 p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
404 p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
407 p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A Dlpddr4_dvfs.c18 while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) in lpddr4_mr_write()
73 val = mmio_read_32(DDRC_MRSTAT(0)); in lpddr4_swffc()
81 val = mmio_read_32(DDRC_PSTAT(0)); in lpddr4_swffc()
102 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
106 val = mmio_read_32(DDRC_DERATEEN(0)); in lpddr4_swffc()
128 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
137 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
145 val = mmio_read_32(DDRC_DBGCAM(0)); in lpddr4_swffc()
158 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
221 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
[all …]
A Dddr4_dvfs.c20 while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) { in ddr4_mr_write()
28 val = mmio_read_32(DDRC_DIMMCTL(0)); in ddr4_mr_write()
51 while (mmio_read_32(DDRC_MRSTAT(0))) { in ddr4_mr_write()
91 val = mmio_read_32(DDRC_RFSHCTL3(0)); in sw_pstate()
108 while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { in sw_pstate()
118 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { in sw_pstate()
134 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) == 0x23) { in sw_pstate()
160 while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) { in ddr4_swffc()
192 while ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) { in ddr4_swffc()
206 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) != 0x23) { in ddr4_swffc()
[all …]
A Ddram_retention.c31 while (mmio_read_32(DDRC_DBGCAM(0)) != DBGCAM_EMPTY) { in dram_enter_retention()
38 while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) { in dram_enter_retention()
51 while (0x23 != (mmio_read_32(DDRC_STAT(0)) & 0x3f)) { in dram_enter_retention()
61 while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { in dram_enter_retention()
67 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { in dram_enter_retention()
83 while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) { in dram_enter_retention()
90 while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) { in dram_enter_retention()
128 while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) { in dram_exit_retention()
171 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { in dram_exit_retention()
183 while (!(mmio_read_32(DDRC_SWSTAT(0)) & 0x1)) { in dram_exit_retention()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/
A Dplat_debug.c18 mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS)); in circular_buffer_setup()
26 sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
29 sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
33 (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4)); in circular_buffer_unlock()
48 mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2)); in clear_all_on_mux()
50 mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1)); in clear_all_on_mux()
57 mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN); in l2c_parity_check_setup()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_internal.c119 mmio_read_32(SYS_TIMER_VALUE_H)); in __spm_output_wake_reason()
122 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); in __spm_output_wake_reason()
407 wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT); in __spm_get_wakeup_status()
408 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA); in __spm_get_wakeup_status()
409 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); in __spm_get_wakeup_status()
413 wakesta->src_req = mmio_read_32(SPM_SRC_REQ); in __spm_get_wakeup_status()
422 wakesta->r13 = mmio_read_32(PCM_REG13_DATA); in __spm_get_wakeup_status()
448 wakesta->isr = mmio_read_32(SPM_IRQ_STA); in __spm_get_wakeup_status()
465 mmio_read_32(SPM_WAKEUP_STA) | in __spm_clean_after_wakeup()
466 mmio_read_32(SPM_BK_WAKE_EVENT)); in __spm_clean_after_wakeup()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/mcsi/
A Dmcsi.c46 if ((mmio_read_32(cci_base_addr + FLUSH_SF) & 0x1) == 0x0) in mcsi_cache_flush()
85 support_ability = mmio_read_32(slave_base); in cci_enable_cluster_coherency()
87 pending = (mmio_read_32( in cci_enable_cluster_coherency()
90 pending = (mmio_read_32( in cci_enable_cluster_coherency()
102 while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING) in cci_enable_cluster_coherency()
121 config = mmio_read_32(slave_base); in cci_disable_cluster_coherency()
140 config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG); in cci_secure_switch()
152 config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG); in cci_pmu_secure_switch()
166 while (mmio_read_32(cci_base_addr + SF_INIT_REG) & TRIG_SF1_INIT) in cci_init_sf()
172 while (mmio_read_32(cci_base_addr + SF_INIT_REG) & TRIG_SF2_INIT) in cci_init_sf()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/
A Dmtk_apusys.c48 mmio_read_32(REVISER_SECUREFW_CTXT), in apusys_kernel_ctrl()
49 mmio_read_32(REVISER_USDRFW_CTXT)); in apusys_kernel_ctrl()
51 mmio_read_32(AO_SEC_FW), in apusys_kernel_ctrl()
52 mmio_read_32(AO_SEC_USR_FW), in apusys_kernel_ctrl()
53 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
54 mmio_read_32(AO_MD32_PRE_DEFINE), in apusys_kernel_ctrl()
55 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
62 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
63 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/apusys/
A Dmtk_apusys.c46 mmio_read_32(REVISER_SECUREFW_CTXT), in apusys_kernel_ctrl()
47 mmio_read_32(REVISER_USDRFW_CTXT)); in apusys_kernel_ctrl()
49 mmio_read_32(AO_SEC_FW), in apusys_kernel_ctrl()
50 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
51 mmio_read_32(AO_MD32_PRE_DEFINE), in apusys_kernel_ctrl()
52 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
59 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
60 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_internal.c112 mmio_read_32(SYS_TIMER_VALUE_H)); in __spm_output_wake_reason()
115 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); in __spm_output_wake_reason()
445 wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT); in __spm_get_wakeup_status()
446 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA); in __spm_get_wakeup_status()
447 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); in __spm_get_wakeup_status()
451 wakesta->src_req = mmio_read_32(SPM_SRC_REQ); in __spm_get_wakeup_status()
460 wakesta->r13 = mmio_read_32(PCM_REG13_DATA); in __spm_get_wakeup_status()
486 wakesta->isr = mmio_read_32(SPM_IRQ_STA); in __spm_get_wakeup_status()
503 mmio_read_32(SPM_WAKEUP_STA) | in __spm_clean_after_wakeup()
504 mmio_read_32(SPM_BK_WAKE_EVENT)); in __spm_clean_after_wakeup()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/audio/mt8188/
A Daudio_domain.c20 uint32_t val = mmio_read_32(PWR_STATUS); in set_audio_domain_sidebands()
37 mmio_read_32(AFE_SE_SECURE_CON), in set_audio_domain_sidebands()
38 mmio_read_32(AFE_SECURE_SIDEBAND0), in set_audio_domain_sidebands()
39 mmio_read_32(AFE_SECURE_SIDEBAND1), in set_audio_domain_sidebands()
40 mmio_read_32(AFE_SECURE_SIDEBAND2), in set_audio_domain_sidebands()
41 mmio_read_32(AFE_SECURE_SIDEBAND3)); in set_audio_domain_sidebands()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/
A Dmt_spm_internal.c101 mmio_read_32(SYS_TIMER_VALUE_H)); in __spm_output_wake_reason()
104 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); in __spm_output_wake_reason()
479 wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT); in __spm_get_wakeup_status()
480 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA); in __spm_get_wakeup_status()
481 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); in __spm_get_wakeup_status()
485 wakesta->src_req = mmio_read_32(SPM_SRC_REQ); in __spm_get_wakeup_status()
494 wakesta->r13 = mmio_read_32(PCM_REG13_DATA); in __spm_get_wakeup_status()
520 wakesta->isr = mmio_read_32(SPM_IRQ_STA); in __spm_get_wakeup_status()
537 (mmio_read_32(SPM_WAKEUP_STA) | in __spm_clean_after_wakeup()
538 mmio_read_32(SPM_BK_WAKE_EVENT))); in __spm_clean_after_wakeup()
[all …]
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/m0/src/
A Ddram.c18 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); in idle_port()
23 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in idle_port()
33 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in deidle_port()
47 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); in ddr_set_pll()
49 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); in ddr_set_pll()
52 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) in ddr_set_pll()
67 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); in m0_main()
68 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) in m0_main()
73 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) in m0_main()
/arm-trusted-firmware-2.8.0/plat/marvell/armada/a8k/common/
A Dplat_pm_trace.c37 mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE); in pm_core_0_trace()
40 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_0_trace()
52 mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE); in pm_core_1_trace()
55 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_1_trace()
67 mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE); in pm_core_2_trace()
70 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_2_trace()
82 mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE); in pm_core_3_trace()
85 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_3_trace()
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/
A Ddram.c19 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); in dram_init()
22 sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >> in dram_init()
40 ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF); in dram_init()
42 noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
44 noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
46 noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
48 noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
50 noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE); in dram_init()
51 noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0); in dram_init()
/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/uart/
A Duart.c70 uart->registers.lcr = mmio_read_32(UART_LCR(base)); in mt_uart_save()
73 uart->registers.efr = mmio_read_32(UART_EFR(base)); in mt_uart_save()
75 uart->registers.fcr = mmio_read_32(UART_FCR_RD(base)); in mt_uart_save()
83 uart->registers.dll = mmio_read_32(UART_DLL(base)); in mt_uart_save()
84 uart->registers.dlh = mmio_read_32(UART_DLH(base)); in mt_uart_save()
86 uart->registers.sample_count = mmio_read_32( in mt_uart_save()
88 uart->registers.sample_point = mmio_read_32( in mt_uart_save()
90 uart->registers.guard = mmio_read_32(UART_GUARD(base)); in mt_uart_save()
94 uart->registers.mcr = mmio_read_32(UART_MCR(base)); in mt_uart_save()
95 uart->registers.ier = mmio_read_32(UART_IER(base)); in mt_uart_save()
[all …]
/arm-trusted-firmware-2.8.0/drivers/arm/gic/v2/
A Dgicv2_private.h32 return mmio_read_32(base + GICD_PIDR2_GICV2); in gicd_read_pidr2()
62 return mmio_read_32(base + GICC_CTLR); in gicc_read_ctlr()
67 return mmio_read_32(base + GICC_PMR); in gicc_read_pmr()
72 return mmio_read_32(base + GICC_BPR); in gicc_read_BPR()
77 return mmio_read_32(base + GICC_IAR); in gicc_read_IAR()
82 return mmio_read_32(base + GICC_EOIR); in gicc_read_EOIR()
87 return mmio_read_32(base + GICC_HPPIR); in gicc_read_hppir()
92 return mmio_read_32(base + GICC_AHPPIR); in gicc_read_ahppir()
97 return mmio_read_32(base + GICC_DIR); in gicc_read_dir()
102 return mmio_read_32(base + GICC_IIDR); in gicc_read_iidr()
[all …]
/arm-trusted-firmware-2.8.0/drivers/renesas/common/ddr/ddr_a/
A Dddr_init_d3.c188 r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; in init_ddr_d3_1866()
190 r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; in init_ddr_d3_1866()
237 r2 = mmio_read_32(DBSC_DBPDRGD_0); in init_ddr_d3_1866()
242 r2 = mmio_read_32(DBSC_DBPDRGD_0); in init_ddr_d3_1866()
261 r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; in init_ddr_d3_1866()
264 r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; in init_ddr_d3_1866()
537 r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; in init_ddr_d3_1600()
583 r2 = mmio_read_32(DBSC_DBPDRGD_0); in init_ddr_d3_1600()
587 r2 = mmio_read_32(DBSC_DBPDRGD_0); in init_ddr_d3_1600()
716 reg = mmio_read_32(PRR); in rcar_dram_init()
[all …]
A Dddr_init_e3.c70 while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) in init_ddr()
88 r2 = mmio_read_32(0xE6790614); in init_ddr()
380 r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; in init_ddr()
382 r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; in init_ddr()
573 r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; in init_ddr()
575 r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; in init_ddr()
662 regval = mmio_read_32(DBSC_DBPDRGD_0) & in init_ddr()
761 regval = mmio_read_32(0x40000000); in init_ddr()
891 r2 = mmio_read_32(0xE6790614); in recovery_from_backup_mode()
1254 r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; in recovery_from_backup_mode()
[all …]
/arm-trusted-firmware-2.8.0/plat/intel/soc/agilex/soc/
A Dagilex_memory_controller.c78 hmc_clk = mmio_read_32(AGX_SYSMGR_CORE_HMC_CLK); in check_hmc_clk()
184 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
187 data = mmio_read_32(AGX_MPFE_IOHMC_DRAMADDRW); in configure_ddr_sched_ctrl_regs()
210 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING0); in configure_ddr_sched_ctrl_regs()
215 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING1); in configure_ddr_sched_ctrl_regs()
220 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING2); in configure_ddr_sched_ctrl_regs()
223 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING3); in configure_ddr_sched_ctrl_regs()
227 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING4); in configure_ddr_sched_ctrl_regs()
233 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG0); in configure_ddr_sched_ctrl_regs()
238 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG0); in configure_ddr_sched_ctrl_regs()
[all …]
/arm-trusted-firmware-2.8.0/drivers/rpi3/sdhost/
A Drpi3_sdhost.c143 mmio_read_32(reg_base + HC_DATAPORT); in rpi3_drain_fifo()
150 edm = mmio_read_32(reg_base + HC_DEBUG); in rpi3_drain_fifo()
181 mmio_read_32(reg_base + HC_COMMAND)); in rpi3_sdhost_print_regs()
183 mmio_read_32(reg_base + HC_ARGUMENT)); in rpi3_sdhost_print_regs()
189 mmio_read_32(reg_base + HC_RESPONSE_0)); in rpi3_sdhost_print_regs()
191 mmio_read_32(reg_base + HC_RESPONSE_1)); in rpi3_sdhost_print_regs()
199 mmio_read_32(reg_base + HC_POWER)); in rpi3_sdhost_print_regs()
201 mmio_read_32(reg_base + HC_DEBUG)); in rpi3_sdhost_print_regs()
205 mmio_read_32(reg_base + HC_BLOCKSIZE)); in rpi3_sdhost_print_regs()
230 dbg = mmio_read_32(reg_base + HC_DEBUG); in rpi3_sdhost_reset()
[all …]
/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/src/
A Dbl31_setup.c409 mmio_read_32(smmu_base + 0x0), in brcm_stingray_smmu_init()
410 mmio_read_32(smmu_base + 0x4), in brcm_stingray_smmu_init()
411 mmio_read_32(smmu_base + 0x8)); in brcm_stingray_smmu_init()
414 mmio_read_32(smmu_base + 0x20), in brcm_stingray_smmu_init()
415 mmio_read_32(smmu_base + 0x24), in brcm_stingray_smmu_init()
416 mmio_read_32(smmu_base + 0x28)); in brcm_stingray_smmu_init()
419 mmio_read_32(smmu_base + 0x2c), in brcm_stingray_smmu_init()
420 mmio_read_32(smmu_base + 0x30), in brcm_stingray_smmu_init()
421 mmio_read_32(smmu_base + 0x34)); in brcm_stingray_smmu_init()
424 mmio_read_32(smmu_base + 0x38), in brcm_stingray_smmu_init()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spm/
A Dspm.c259 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) in spm_set_pcm_wdt()
279 wakesta->r12 = mmio_read_32(SPM_SW_RSV_0); in spm_get_wakeup_status()
281 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); in spm_get_wakeup_status()
285 wakesta->r13 = mmio_read_32(PCM_REG13_DATA); in spm_get_wakeup_status()
287 wakesta->req_sta = mmio_read_32(SRC_REQ_STA); in spm_get_wakeup_status()
288 wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG); in spm_get_wakeup_status()
289 wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2); in spm_get_wakeup_status()
290 wakesta->r15 = mmio_read_32(PCM_REG15_DATA); in spm_get_wakeup_status()
294 wakesta->isr = mmio_read_32(SPM_IRQ_STA); in spm_get_wakeup_status()
300 mmio_read_32(SPM_WAKEUP_STA) | in spm_clean_after_wakeup()
[all …]

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