| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/include/ |
| A D | plat_macros.S | 24 mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
32 mov_imm x17, BASE_GICC_BASE
33 mov_imm x16, BASE_GICD_BASE
36 mov_imm x17, VE_GICC_BASE
37 mov_imm x16, VE_GICD_BASE
|
| /arm-trusted-firmware-2.8.0/plat/intel/soc/common/aarch64/ |
| A D | plat_helpers.S | 38 mov_imm x0, PLAT_SEC_ENTRY
40 mov_imm x2, PLAT_CPUID_RELEASE
73 mov_imm x1, PLAT_SEC_ENTRY
91 mov_imm x1, PLAT_SEC_ENTRY
105 mov_imm x0, CRASH_CONSOLE_BASE
106 mov_imm x1, PLAT_UART_CLOCK
107 mov_imm x2, PLAT_BAUDRATE
119 mov_imm x1, CRASH_CONSOLE_BASE
124 mov_imm x0, CRASH_CONSOLE_BASE
|
| /arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/aarch64/ |
| A D | poplar_helpers.S | 49 mov_imm x0, POPLAR_CRASH_UART_BASE
50 mov_imm x1, POPLAR_CRASH_UART_CLK_IN_HZ
51 mov_imm x2, POPLAR_CONSOLE_BAUDRATE
63 mov_imm x1, POPLAR_CRASH_UART_BASE
76 mov_imm x0, POPLAR_CRASH_UART_BASE
|
| /arm-trusted-firmware-2.8.0/plat/qemu/common/aarch32/ |
| A D | plat_helpers.S | 70 mov_imm r2, PLAT_QEMU_HOLD_BASE
83 mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
109 mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
110 mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
111 mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE
123 mov_imm r1, PLAT_QEMU_CRASH_UART_BASE
136 mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
|
| /arm-trusted-firmware-2.8.0/plat/qemu/common/aarch64/ |
| A D | plat_helpers.S | 68 mov_imm x2, PLAT_QEMU_HOLD_BASE
80 mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
106 mov_imm x0, PLAT_QEMU_CRASH_UART_BASE
107 mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
108 mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE
120 mov_imm x1, PLAT_QEMU_CRASH_UART_BASE
133 mov_imm x0, PLAT_QEMU_CRASH_UART_BASE
|
| /arm-trusted-firmware-2.8.0/plat/socionext/synquacer/ |
| A D | sq_helpers.S | 50 mov_imm x0, BL2_MAILBOX_BASE
88 mov_imm x0, PLAT_SQ_BOOT_UART_BASE
89 mov_imm x1, PLAT_SQ_BOOT_UART_CLK_IN_HZ
90 mov_imm x2, SQ_CONSOLE_BAUDRATE
101 mov_imm x1, PLAT_SQ_BOOT_UART_BASE
113 mov_imm x0, PLAT_SQ_BOOT_UART_BASE
|
| /arm-trusted-firmware-2.8.0/plat/amlogic/common/aarch64/ |
| A D | aml_helpers.S | 64 mov_imm x0, AML_UART0_AO_BASE
65 mov_imm x1, AML_UART0_AO_CLK_IN_HZ
66 mov_imm x2, AML_UART_BAUDRATE
76 mov_imm x1, AML_UART0_AO_BASE
87 mov_imm x0, AML_UART0_AO_BASE
|
| /arm-trusted-firmware-2.8.0/lib/extensions/mtpmu/aarch64/ |
| A D | mtpmu.S | 29 mov_imm x1, ID_AA64DFR0_MTPMU_MASK
65 mov_imm x0, ID_AA64PFR0_EL3_SHIFT
71 mov_imm x1, MDCR_MTPME_BIT
85 mov_imm x0, ID_AA64PFR0_EL2_SHIFT
91 mov_imm x1, MDCR_EL2_MTPME
|
| /arm-trusted-firmware-2.8.0/plat/arm/common/aarch64/ |
| A D | arm_helpers.S | 50 mov_imm x0, PLAT_ARM_CRASH_UART_BASE
51 mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ
52 mov_imm x2, ARM_CONSOLE_BAUDRATE
64 mov_imm x1, PLAT_ARM_CRASH_UART_BASE
77 mov_imm x0, PLAT_ARM_CRASH_UART_BASE
|
| /arm-trusted-firmware-2.8.0/plat/imx/imx7/common/ |
| A D | imx7_helpers.S | 38 mov_imm r0, PLAT_IMX7_BOOT_UART_BASE
39 mov_imm r1, PLAT_IMX7_BOOT_UART_CLK_IN_HZ
40 mov_imm r2, PLAT_IMX7_CONSOLE_BAUDRATE
45 mov_imm r1, PLAT_IMX7_BOOT_UART_BASE
|
| /arm-trusted-firmware-2.8.0/plat/allwinner/common/ |
| A D | plat_helpers.S | 20 mov_imm x0, SUNXI_UART0_BASE
21 mov_imm x1, SUNXI_UART0_CLK_IN_HZ
22 mov_imm x2, SUNXI_UART0_BAUDRATE
27 mov_imm x1, SUNXI_UART0_BASE
|
| /arm-trusted-firmware-2.8.0/plat/ti/k3/common/ |
| A D | k3_helpers.S | 123 mov_imm x0, CRASH_CONSOLE_BASE
124 mov_imm x1, CRASH_CONSOLE_CLK
125 mov_imm x2, CRASH_CONSOLE_BAUD_RATE
139 mov_imm x1, CRASH_CONSOLE_BASE
153 mov_imm x0, CRASH_CONSOLE_BASE
|
| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp_r/ |
| A D | fvp_r_helpers.S | 41 mov_imm x1, PWRC_BASE
80 mov_imm x1, PWRC_BASE
100 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
123 mov_imm x1, MPIDR_AFFINITY_MASK
|
| /arm-trusted-firmware-2.8.0/plat/renesas/common/include/ |
| A D | plat_macros.S | 31 mov_imm x17, RCAR_GICC_BASE
32 mov_imm x16, RCAR_GICD_BASE
76 mov_imm x7, (CCI500_BASE + SLAVE_IFACE3_OFFSET)
79 mov_imm x7, (CCI500_BASE + SLAVE_IFACE4_OFFSET)
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/include/ |
| A D | plat_macros.S | 35 mov_imm x16, BASE_GICD_BASE
36 mov_imm x17, BASE_GICC_BASE
69 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
73 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/include/ |
| A D | plat_macros.S | 35 mov_imm x26, BASE_GICD_BASE
36 mov_imm x27, BASE_GICC_BASE
69 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
73 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
|
| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/include/ |
| A D | plat_macros.S | 36 mov_imm x16, PLAT_ARM_GICD_BASE
37 mov_imm x17, PLAT_ARM_GICC_BASE
67 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
71 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
|
| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/include/ |
| A D | plat_macros.S | 36 mov_imm x16, GICD_REG_BASE
37 mov_imm x17, GICC_REG_BASE
67 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
71 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
|
| /arm-trusted-firmware-2.8.0/plat/allwinner/common/include/ |
| A D | plat_macros.S | 22 mov_imm x17, SUNXI_GICC_BASE
23 mov_imm x16, SUNXI_GICD_BASE
|
| /arm-trusted-firmware-2.8.0/plat/qemu/common/include/ |
| A D | plat_macros.S | 21 mov_imm x17, GICC_BASE
22 mov_imm x16, GICD_BASE
|
| /arm-trusted-firmware-2.8.0/plat/qti/msm8916/include/ |
| A D | plat_macros.S | 22 mov_imm x16, APCS_QGIC2_GICD
23 mov_imm x17, APCS_QGIC2_GICC
|
| /arm-trusted-firmware-2.8.0/include/plat/arm/css/common/aarch64/ |
| A D | css_macros.S | 20 mov_imm x16, PLAT_ARM_GICD_BASE
21 mov_imm x17, PLAT_ARM_GICC_BASE
|
| /arm-trusted-firmware-2.8.0/plat/arm/board/arm_fpga/ |
| A D | rom_trampoline.S | 22 mov_imm x1, BL31_BASE /* beginning of DRAM */
23 mov_imm x0, FPGA_PRELOADED_DTB_BASE
|
| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/aarch64/ |
| A D | fvp_helpers.S | 41 mov_imm x1, PWRC_BASE
54 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
92 mov_imm x1, PWRC_BASE
112 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
135 mov_imm x1, MPIDR_AFFINITY_MASK
|
| /arm-trusted-firmware-2.8.0/plat/arm/board/juno/aarch64/ |
| A D | juno_helpers.S | 159 mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
216 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
229 mov_imm \_reg_d, (0xe3000000 | \
239 mov_imm \_reg_d, (0xe3400000 | \
264 mov_imm w2, 0xe12fff10
267 mov_imm x3, HI_VECTOR_BASE
|