| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/ |
| A D | plat_sip_calls.c | 44 uint64_t per[3] = {0ULL}; in plat_sip_handler() local
63 per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U); in plat_sip_handler()
64 per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U); in plat_sip_handler()
65 per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U); in plat_sip_handler()
68 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); in plat_sip_handler()
69 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); in plat_sip_handler()
70 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); in plat_sip_handler()
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | fvp-base-gicv3-psci-1t.dts | 7 /* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
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| A D | fvp-base-gicv3-psci-dynamiq-2t.dts | 7 /* DynamIQ configuration: 1 cluster with up to 8 CPUs with 2 threads per each */
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| A D | fvp-base-psci-common.dtsi | 80 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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| A D | fvp-defs.dtsi | 319 /* Max 4 CPUs per cluster */
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| /arm-trusted-firmware-2.8.0/docs/components/fconf/ |
| A D | mpmm-bindings.rst | 5 DTB bindings allow the platform to communicate per-core support for |MPMM| via
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| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/scat/ |
| A D | bl31.scat | 193 /* padded memory section to store per cpu bakery locks */
225 /* padded memory section to store per cpu timestamps */
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | mpmm.rst | 11 |MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
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| A D | rmm-el3-comms-spec.rst | 135 At warm boot, RMM is already initialized and only some per-CPU initialization
153 as per the following table:
499 As per SMCCCv1.2, x4 must be preserved if not being used as return argument by the SMC function
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| A D | granule-protection-tables-design.rst | 235 And solve to get 0x20000 bytes per L1 table.
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| A D | secure-partition-manager.rst | 581 be provided per SP. The memory region node as defined in the specification
714 FFA_NOTIFICATION_BITMAP_CREATE to allocate the notifications bitmap per FF-A
931 per-vCPU notifications targeted to the current vCPU.
1123 interrupt as per the guidance provided by FF-A v1.1 EAC0 specification.
1140 SPMC as per the guidance provided by FF-A v1.1 EAC0 specification.
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| /arm-trusted-firmware-2.8.0/ |
| A D | .editorconfig | 66 # "Use 4 spaces per indentation level."
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | firmware-design.rst | 552 BL31 initializes the per-CPU data framework, which provides a cache of
976 Function ID is passed in W0 from the lower exception level (as per the
2148 Depending upon the data cache line size, the per-CPU fields of the
2198 | `bakery_info_t`| <-- Lock_0 per-CPU field
2201 | `bakery_info_t`| <-- Lock_1 per-CPU field
2206 | `bakery_info_t`| <-- Lock_N per-CPU field
2214 | `bakery_info_t`| <-- Lock_0 per-CPU field
2217 | `bakery_info_t`| <-- Lock_1 per-CPU field
2222 | `bakery_info_t`| <-- Lock_N per-CPU field
2519 PMF timestamps are stored in a per-service timestamp region. On a
[all …]
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| A D | interrupt-framework-design.rst | 328 interrupt was generated and routed as per the routing model specified
510 will be routed to EL3 (as per the routing model where **CSS=1 and
534 If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
635 upon exception entry. The registers are saved in the per-cpu ``cpu_context``
639 per-cpu ``cpu_context`` data structure referenced by the ``SP_EL3`` register.
642 from the per-cpu ``cpu_context`` data structure in ``SP_EL0`` and
675 The handler function returns a reference to the per-cpu ``cpu_context_t``
728 per the synchronous interrupt handling model it implements. A Secure-EL1
735 #. Setting the return value of the handler to the per-cpu ``cpu_context`` if
787 #. It returns the per-cpu ``cpu_context`` to indicate that the interrupt can
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| A D | auth-framework.rst | 140 #. Check the integrity of the image as per its type.
142 #. Authenticate the image as per the cryptographic algorithms used.
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | poplar.rst | 12 video at 60 frames per second.
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| A D | allwinner.rst | 11 There is one build target per supported SoC:
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| A D | nvidia-tegra.rst | 35 micro-ops can be executed per clock), and includes a 128KB 4-way L1
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 31 As per the `SMC Calling Convention`_, up to 4 values may be returned to the
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| /arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/ |
| A D | porting.rst | 113 The PHY porting layer simplifies updating static values per board type,
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 63 #. On receipt of an SMC, save the register context as per `SMCCC`_.
71 X0 (AArch64) and restore other registers as per `SMCCC`_.
299 cpu operations (cpu_ops) and per-cpu data framework. Other helper library
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| A D | build-options.rst | 204 feature as per TBBR.
538 unique per device.
543 tool to create certificates as per the Chain of Trust described in
670 the measurements and recording them as per `PSA DRTM specification`_. For
720 - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
1145 firmware bank. Each firmware bank must have the same number of images as per
1150 - ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
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| A D | porting-guide.rst | 172 Defines the maximum number of local power states per power domain level
452 Optional flag that can be set per-image to enable the dynamic allocation of
511 If the platform needs to allocate data within the per-cpu data framework in
515 required memory within the the per-cpu data to minimize wastage.
519 Defines the memory (in bytes) to be reserved within the per-cpu data
1036 per-CPU stacks). This function will be invoked very early in the
2410 bytes) aligned to the cache line boundary that should be allocated per-cpu to
2418 accessing per-cpu bakery lock information.
3504 amount of open resources per driver.
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| A D | rt-svc-writers-guide.rst | 173 If the service uses per-CPU data this must either be initialized for all CPUs
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | context_mgmt_rework.rst | 61 The CPU context contains some EL3 sysregs and gets applied on a per-world
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