| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/soc/ |
| A D | soc.c | 55 if (pll_id == PPLL_ID) in set_pll_slow_mode()
64 if (pll_id == PPLL_ID) in set_pll_normal_mode()
71 static void set_pll_bypass(uint32_t pll_id) in set_pll_bypass() argument
73 if (pll_id == PPLL_ID) in set_pll_bypass()
81 static void _pll_suspend(uint32_t pll_id) in _pll_suspend() argument
83 set_pll_slow_mode(pll_id); in _pll_suspend()
84 set_pll_bypass(pll_id); in _pll_suspend()
220 if (pll_id == PPLL_ID) in set_plls_nobypass()
228 static void _pll_resume(uint32_t pll_id) in _pll_resume() argument
230 set_plls_nobypass(pll_id); in _pll_resume()
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| A D | soc.h | 16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/soc/ |
| A D | soc.c | 125 static void plls_suspend(uint32_t pll_id) in plls_suspend() argument
127 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in plls_suspend()
128 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in plls_suspend()
129 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in plls_suspend()
130 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in plls_suspend()
132 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); in plls_suspend()
133 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); in plls_suspend()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/pmu/ |
| A D | pmu.c | 281 ERROR("lock-pll: %d\n", pll_id); in pm_pll_wait_lock()
286 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
289 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
292 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
340 static inline void pll_suspend(uint32_t pll_id) in pll_suspend() argument
349 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
353 pll_pwr_dwn(pll_id, pmu_pd_off); in pll_suspend()
356 static inline void pll_resume(uint32_t pll_id) in pll_resume() argument
358 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_resume()
361 pm_pll_wait_lock(pll_id); in pll_resume()
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| A D | pmu.h | 116 #define PLL_IS_NORM_MODE(mode, pll_id) \ argument
117 ((mode & (PLL_NORM_MODE(pll_id)) & 0xffff) != 0)
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3288/drivers/soc/ |
| A D | soc.c | 105 static void pll_save(uint32_t pll_id) in pll_save() argument
107 uint32_t *pll = slp_data.pll_con[pll_id]; in pll_save()
109 pll[0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in pll_save()
110 pll[1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in pll_save()
111 pll[2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in pll_save()
112 pll[3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in pll_save()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/px30/drivers/pmu/ |
| A D | pmu.c | 867 ERROR("Can't wait pll:%d lock\n", pll_id); in pm_pll_wait_lock()
886 if (pll_id != GPLL_ID) in pll_set_mode()
893 static inline void pll_suspend(uint32_t pll_id) in pll_suspend() argument
898 if (pll_id != GPLL_ID) in pll_suspend()
899 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_suspend()
905 ddr_data.cru_plls_con_save[pll_id][i] = in pll_suspend()
909 pll_set_mode(pll_id, SLOW_MODE); in pll_suspend()
912 static inline void pll_resume(uint32_t pll_id) in pll_resume() argument
916 if (pll_id != GPLL_ID) { in pll_resume()
926 pm_pll_wait_lock(pll_base, pll_id); in pll_resume()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/ |
| A D | suspend.c | 653 __pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src) in pmusram_restore_pll() argument
655 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
657 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
658 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
659 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
660 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
661 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
663 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
665 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
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| /arm-trusted-firmware-2.8.0/drivers/st/clk/ |
| A D | stm32mp1_clk.c | 833 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq()
1472 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_check_pll_conf()
1545 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_pll_start()
1565 pll_id, pllxcr, mmio_read_32(pllxcr)); in stm32mp1_pll_output()
1594 pll_id, pllxcr, mmio_read_32(pllxcr)); in stm32mp1_pll_stop()
1661 stm32mp1_pll_config_output(pll_id, pllcfg); in stm32mp1_pll_config()
2177 enum stm32mp1_pll_id pll_id; in get_parent_id_parent() local
2190 pll_id = _PLL1; in get_parent_id_parent()
2195 pll_id = _PLL2; in get_parent_id_parent()
2200 pll_id = _PLL3; in get_parent_id_parent()
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| A D | clk-stm32mp13.c | 1632 int pll_id; member
1640 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_recalc_rate()
1677 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_is_enabled()
1686 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_enable()
1695 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); in clk_stm32_pll_disable()
1712 .pll_id = _pll_id,\
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/pmu/ |
| A D | pmu.c | 565 uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st; in clst_pwr_domain_suspend() local
571 pll_id = ALPLL_ID; in clst_pwr_domain_suspend()
574 pll_id = ABPLL_ID; in clst_pwr_domain_suspend()
586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
589 clst_warmboot_data[pll_id] = PMU_CLST_RET; in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
601 clst_warmboot_data[pll_id] = 0; in clst_pwr_domain_suspend()
609 uint32_t pll_id, pll_st; in clst_pwr_domain_resume() local
615 pll_id = ALPLL_ID; in clst_pwr_domain_resume()
617 pll_id = ABPLL_ID; in clst_pwr_domain_resume()
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