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Searched refs:pll_set_rate_mode (Results 1 – 4 of 4) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/
A Dapupwr_clkctl.h22 enum pll_set_rate_mode mode, int32_t freq);
A Dapupwr_clkctl_def.h52 enum pll_set_rate_mode { enum
A Dapupwr_clkctl.c19 enum pll_set_rate_mode PLL_MODE = CON0_PCW;
A Dapupll.c508 enum pll_set_rate_mode mode, int32_t freq) in anpu_pll_set_rate()

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