| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | psci-pd-tree.rst | 20 levels in the power domain tree to four.
23 mechanism used to populate the power domain topology tree.
36 #. The attributes of a core power domain differ from the attributes of power
39 performing a power management operation on the core power domain.
50 Describing a power domain tree
63 of power domains that are its direct children.
66 non-leaf power domains.
188 * CPU power domain i.e. non-leaf nodes.
204 /* Index of the parent power domain node */
213 /* Index of the parent power domain node */
[all …]
|
| A D | firmware-design.rst | 14 implementing power management use-cases (for example, secondary CPU boot,
579 - Initialize the power controller device.
730 the platform power management code with a Warm boot initialization
1111 the TSP to prepare for or respond to the power state change
1357 #. Processor specific power down sequences.
1421 CPU specific power down sequence
1426 retrieved during power down sequences.
1428 Various CPU drivers register handlers to perform power down at certain power
1430 request, determines the highest power level at which to execute power down
1440 turning off CCI coherency during a cluster power down.
[all …]
|
| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | mpmm.rst | 4 |MPMM| is an optional microarchitectural power management mechanism supported by
7 assist in |SoC| processor power domain dynamic power budgeting and limit the
25 external power controller can use these metrics to budget SoC power by
|
| A D | ffa-manifest-binding.rst | 164 - power-management-messages
166 - Specifies which power management messages a partition subscribes to.
167 A set bit means the partition should be informed of the power event, clear
|
| /arm-trusted-firmware-2.8.0/docs/perf/ |
| A D | psci-performance-juno.rst | 25 Juno supports CPU, cluster and system power down states, corresponding to power
67 power state to exiting the TF PSCI implementation. This corresponds to:
85 ``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
117 ``CPU_SUSPEND`` to power level 0 on all CPUs in parallel
141 effectively serializes the SCP power down commands from all CPUs.
143 On platforms with a more efficient CPU power down mechanism, it should be
147 require locks at power level 0.
150 the cache associated with power level 0 is flushed (L1).
152 ``CPU_SUSPEND`` to deepest power level on all CPUs in sequence
184 ``CPU_SUSPEND`` to power level 0 on all CPUs in sequence
[all …]
|
| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | xilinx-zynqmp.rst | 56 The following power domain tree represents the power domain model used by TF-A
72 The 4 leaf power domains represent the individual A53 cores, while resources
73 common to the cluster are grouped in the power domain on the top.
|
| A D | allwinner.rst | 48 to be loaded into the ARISC SCP (A64, H5), or the power sequence control
57 This allows more advanced power saving techniques, like suspend to RAM.
64 power management controller, BL31 tries to set up all needed power rails,
66 software like U-Boot to ignore power control via the PMIC.
|
| A D | nvidia-tegra.rst | 53 Denver also features new low latency power-state transitions, in addition
54 to extensive power-gating and dynamic voltage and clock scaling based on
138 The PSCI implementation expects each platform to expose the 'power state'
148 be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit.
|
| A D | hikey.rst | 122 - Make sure Pin3-Pin4 on J15 are connected for recovery mode. Then power on HiKey.
151 - Make sure Pin3-Pin4 on J15 are open for normal boot mode. Then power on HiKey.
|
| A D | rcar-gen3.rst | 128 Trusted Environment with a modification to support power
134 plat-rcar: cpu-suspend: handle the power level
|
| A D | hikey960.rst | 176 - Make sure "Boot Mode" switch is OFF for normal boot mode. Then power on HiKey960.
|
| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | porting-guide.rst | 148 to know the highest power domain level that it should consider for power
155 Defines the local power state corresponding to the deepest power down
156 possible at every power domain level in the platform. The local power
159 value to initialize the local power states of the power domain nodes and
172 Defines the maximum number of local power states per power domain level
175 power domain level (power-down and retention). If the platform needs to
2576 level. Each entry contains the local power state the power domain at that power
2655 power states.
2659 of the power state i.e. for two power states X & Y, if X < Y
2773 target local power states for the CPU power domain and its parent
[all …]
|
| A D | psci-lib-integration-guide.rst | 34 do bookkeeping for the EL3 Runtime Software during power management.
68 whether the PSCI API resulted in power down of the CPU.
79 be preserved across CPU power down/power up cycles are maintained in
202 - Initializes PSCI power domain and state coordination data structures.
233 As explained in `Secure payload power management callback`_,
432 All platform specific operations for power management are done via
440 Secure payload power management callback
443 During PSCI power management operations, the EL3 Runtime Software may
452 appropriately during CPU power down/power up. Any secure interrupt targeted
454 to power down of the current CPU. During power up, these interrupt can be
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/ |
| A D | mt_spm_vcorefs.c | 455 int power = 0; in spm_vcorefs_vcore_setting() local
477 power = (int)devinfo_table[idx]; in spm_vcorefs_vcore_setting()
480 if (power > 0 && power <= 40) { in spm_vcorefs_vcore_setting()
|
| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/fdts/ |
| A D | fvp_tsp_sp_manifest.dts | 33 power-management-messages = <0x7>;
|
| /arm-trusted-firmware-2.8.0/drivers/st/bsec/ |
| A D | bsec2.c | 28 static uint32_t bsec_power_safmem(bool power);
266 result = bsec_power_safmem((bool)cfg->power & in bsec_set_config()
302 cfg->power = (uint8_t)((value & BSEC_CONF_POWER_UP_MASK) >> in bsec_get_config()
878 static uint32_t bsec_power_safmem(bool power) in bsec_power_safmem() argument
887 if (power) { in bsec_power_safmem()
895 if (power) { in bsec_power_safmem()
|
| /arm-trusted-firmware-2.8.0/plat/allwinner/common/ |
| A D | arisc_off.S | 32 # - Finally turn off the core's power switch by writing 0xff to the
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
74 l.sw 0x1540(r6), r5 # core power switch registers
|
| /arm-trusted-firmware-2.8.0/include/drivers/st/ |
| A D | bsec.h | 81 uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */ member
|
| /arm-trusted-firmware-2.8.0/docs/plat/arm/ |
| A D | arm-build-options.rst | 44 for the construction of composite state-ID in the power-state parameter.
49 field of power-state parameter.
140 instead of SCPI/BOM driver for communicating with the SCP during power
157 require all the CPUs to execute the CPU specific power down sequence to
158 complete a warm reboot sequence in which only the CPUs are power cycled.
|
| /arm-trusted-firmware-2.8.0/docs/about/ |
| A D | features.rst | 17 - Library support for CPU specific reset and power down sequences. This
25 - A generic |SCMI| driver to interface with conforming power controllers, for
31 - |PSCI| library support for CPU, cluster and system power management
|
| /arm-trusted-firmware-2.8.0/docs/plat/arm/tc/ |
| A D | index.rst | 7 to abstract power and system management tasks away from application
|
| /arm-trusted-firmware-2.8.0/docs/plat/nxp/ |
| A D | nxp-layerscape.rst | 13 Layerscape family, combines FinFET process technology's low power and
61 power supply and single clock design. The new 0.9V versions of the LS1043A
62 and LS1023A deliver addition power savings for applications such as Wireless
100 The LS1046A is a cost-effective, power-efficient, and highly integrated
102 line of QorIQ communications processors. Featuring power-efficient 64-bit
|
| /arm-trusted-firmware-2.8.0/docs/ |
| A D | glossary.rst | 111 Maximum Power Mitigation Mechanism, an optional power management mechanism
|
| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | stm32mp157c-ed1.dts | 182 power-off-time-sec = <10>;
|
| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | threat_model_fvp_r.rst | 72 bypassing the signature verification stage using clock- or power-glitching
|