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Searched refs:pwr (Results 1 – 11 of 11) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/cpu_pm/cpcv3_2/
A Dmt_cpu_pm.c112 .pwr = { in cpupm_smp_init()
150 unsigned int stateid = state->pwr.state_id; in mcusys_prepare_suspend()
206 if (!state || (state->pwr.afflv > PLAT_MAX_PWR_LVL)) { in cpupm_do_pstate_off()
210 switch (state->pwr.state_id) { in cpupm_do_pstate_off()
225 !IS_PLAT_SYSTEM_SUSPEND(state->pwr.afflv)) { in cpupm_do_pstate_off()
245 if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) { in cpupm_do_pstate_off()
263 if (state->pwr.afflv > PLAT_MAX_PWR_LVL) { in cpupm_do_pstate_on()
275 if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) { in cpupm_do_pstate_on()
279 switch (state->pwr.state_id) { in cpupm_do_pstate_on()
298 !IS_PLAT_SYSTEM_SUSPEND(state->pwr.afflv)) { in cpupm_do_pstate_on()
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/lib/pm/armv8_2/
A Dpwr_ctrl.c161 if (IS_PLAT_SYSTEM_RETENTION(state->pwr.afflv)) { in armv8_2_cpu_pwr_on_common()
239 .pwr = { in armv8_2_power_domain_on_finish()
264 .pwr = { in armv8_2_power_domain_off()
290 pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid); in armv8_2_power_domain_suspend()
291 pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state); in armv8_2_power_domain_suspend()
292 pm_state.pwr.raw = state; in armv8_2_power_domain_suspend()
328 pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid); in armv8_2_power_domain_suspend_finish()
329 pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state); in armv8_2_power_domain_suspend_finish()
330 pm_state.pwr.raw = state; in armv8_2_power_domain_suspend_finish()
/arm-trusted-firmware-2.8.0/include/drivers/st/
A Dstm32mp_ddr.h50 uintptr_t pwr; member
/arm-trusted-firmware-2.8.0/fdts/
A Dstm32mp151.dtsi206 pwr_regulators: pwr@50001000 {
207 compatible = "st,stm32mp1,pwr-reg";
231 compatible = "st,stm32mp151-pwr-mcu", "syscon";
235 pwr_irq: pwr@50001020 {
236 compatible = "st,stm32mp1-pwr";
250 * EXTI 55 to 60. It's mapped on pwr interrupt
253 exti_pwr: exti-pwr {
A Dfvp-foundation-gicv2-psci.dts46 max-pwr-lvl = <2>;
A Dfvp-foundation-gicv3-psci.dts46 max-pwr-lvl = <2>;
A Dfvp-base-psci-common.dtsi46 max-pwr-lvl = <2>;
A Dstm32mp131.dtsi226 pwr_regulators: pwr@50001000 {
227 compatible = "st,stm32mp1,pwr-reg";
/arm-trusted-firmware-2.8.0/drivers/st/ddr/
A Dstm32mp1_ram.c144 priv->pwr = stm32mp_pwr_base(); in stm32mp1_ddr_probe()
/arm-trusted-firmware-2.8.0/plat/mediatek/lib/pm/
A Dmtk_pm.h99 struct mtk_cpu_pm_state pwr; member
/arm-trusted-firmware-2.8.0/docs/
A Dchange-log.md4428 return value and correctly check pwr-regulators node

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