Searched refs:pwr_domain (Results 1 – 6 of 6) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mn/ |
| A D | gpc.c | 68 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; in imx_gpc_pm_domain_enable() local
71 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
78 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
81 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
84 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
98 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
100 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
115 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
118 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
129 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/ |
| A D | gpc.c | 175 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; in imx_gpc_pm_domain_enable() local
192 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
205 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
208 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
211 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()
234 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
250 if (pwr_domain->always_on) { in imx_gpc_pm_domain_enable()
254 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
259 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
269 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/ |
| A D | gpc.c | 166 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; in imx_gpc_pm_domain_enable() local
179 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
182 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
185 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
248 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
250 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
300 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
302 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
335 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
338 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
[all …]
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| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/ptp3/ |
| A D | ptp3_common.c | 99 if ((data->pwr_domain & MT_CPUPM_PWR_DOMAIN_CORE) > 0) { in ptp3_handle_pwr_on_event()
113 if ((data->pwr_domain & MT_CPUPM_PWR_DOMAIN_CORE) > 0) { in ptp3_handle_pwr_off_event()
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| /arm-trusted-firmware-2.8.0/plat/mediatek/lib/pm/armv8_2/ |
| A D | pwr_ctrl.c | 248 nb.pwr_domain = pstate; in armv8_2_power_domain_on_finish()
272 nb.pwr_domain = pstate; in armv8_2_power_domain_off()
308 nb.pwr_domain = pstate; in armv8_2_power_domain_suspend()
346 nb.pwr_domain = pstate; in armv8_2_power_domain_suspend_finish()
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| /arm-trusted-firmware-2.8.0/plat/mediatek/lib/pm/ |
| A D | mtk_pm.h | 144 unsigned int pwr_domain; member
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