| /arm-trusted-firmware-2.8.0/lib/libc/aarch32/ |
| A D | memset.S | 22 mov r12, r0 /* keep r0 */
29 strbhs r1, [r12], #1
31 tst r12, #3
49 stmiahs r12!, {r1, r3, r4, lr}
50 stmiahs r12!, {r1, r3, r4, lr}
58 strcs r1, [r12], #4 /* write 4 bytes */
60 strhmi r1, [r12], #2 /* write 2 bytes */
62 strbmi r1, [r12] /* write 1 byte */
68 strmi r1, [r12], #4 /* write 4 bytes */
70 strhcs r1, [r12], #2 /* write 2 bytes */
[all …]
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| /arm-trusted-firmware-2.8.0/lib/aarch32/ |
| A D | cache_helpers.S | 93 push {r4-r12, lr}
100 mov r12, r2, LSR r10 // extract cache type bits from clidr
101 and r12, r12, #7 // mask the bits for current cache only
102 cmp r12, #2 // see what cache we have at this level
107 ldcopr r12, CCSIDR // read the new ccsidr
113 ubfx r4, r12, #3, #21 // r4 = associativity CCSIDR[23:3]
116 ubfx r4, r12, #3, #10 // r4 = associativity CCSIDR[12:3]
124 ldcopr r12, CCSIDR2 // FEAT_CCIDX numsets is in CCSIDR2
125 ubfx r7, r12, #0, #24 // r7 = numsets CCSIDR2[23:0]
128 ubfx r7, r12, #13, #15 // r7 = numsets CCSIDR[27:13]
[all …]
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| /arm-trusted-firmware-2.8.0/lib/cpus/aarch32/ |
| A D | cortex_a9.S | 61 push {r12, lr}
73 pop {r12, lr}
89 push {r12, lr}
98 pop {r12, lr}
103 push {r12, lr}
114 pop {r12, lr}
|
| A D | cortex_a12.S | 43 push {r12, lr}
52 pop {r12, lr}
57 push {r12, lr}
68 pop {r12, lr}
|
| A D | cortex_a5.S | 43 push {r12, lr}
52 pop {r12, lr}
57 push {r12, lr}
68 pop {r12, lr}
|
| A D | cortex_a7.S | 43 push {r12, lr}
52 pop {r12, lr}
57 push {r12, lr}
68 pop {r12, lr}
|
| A D | cortex_a32.S | 52 push {r12, lr}
72 pop {r12, lr}
83 push {r12, lr}
116 pop {r12, lr}
|
| A D | cortex_a15.S | 117 push {r12, lr}
131 pop {r12, lr}
159 push {r12, lr}
168 pop {r12, lr}
173 push {r12, lr}
184 pop {r12, lr}
|
| A D | cortex_a17.S | 108 push {r12, lr}
121 pop {r12, lr}
153 push {r12, lr}
162 pop {r12, lr}
167 push {r12, lr}
178 pop {r12, lr}
|
| A D | cortex_a72.S | 147 push {r12, lr}
185 pop {r12, lr}
194 push {r12, lr}
247 pop {r12, lr}
256 push {r12, lr}
270 pop {r12, lr}
|
| A D | cortex_a53.S | 220 push {r12, lr}
240 pop {r12, lr}
250 push {r12, lr}
283 pop {r12, lr}
292 push {r12, lr}
308 pop {r12, lr}
|
| A D | cortex_a57.S | 488 push {r12, lr}
520 pop {r12, lr}
530 push {r12, lr}
575 pop {r12, lr}
584 push {r12, lr}
610 pop {r12, lr}
|
| A D | cpu_helpers.S | 219 push {r4, r5, r12, lr}
262 pop {r4, r5, r12, pc}
|
| /arm-trusted-firmware-2.8.0/include/arch/aarch32/ |
| A D | smccc_macros.S | 21 stm sp, {r0-r12}
71 mrs r12, spsr_svc
72 stm r0!, {r4-r12}
82 mrs r12, spsr
83 stm r0!, {r4-r12}
204 ldm r1!, {r4-r12}
213 msr spsr_svc, r12
215 ldm r1!, {r4-r12}
230 msr spsr_fsxc, r12
237 ldm r0, {r0-r12}
|
| /arm-trusted-firmware-2.8.0/lib/el3_runtime/aarch32/ |
| A D | cpu_data.S | 21 push {r12, lr}
23 pop {r12, lr}
|
| /arm-trusted-firmware-2.8.0/bl2/aarch32/ |
| A D | bl2_el3_entrypoint.S | 20 mov r12, r3
37 mov r3, r12
|
| A D | bl2_entrypoint.S | 35 mov r12, r3
120 mov r3, r12
|
| /arm-trusted-firmware-2.8.0/lib/psci/aarch32/ |
| A D | psci_helpers.S | 64 push {r12, lr}
94 pop {r12, pc}
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/drivers/spm/ |
| A D | spm.c | 211 wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); in spm_get_wakeup_status()
325 wakesta->assert_pc, wakesta->r12, wakesta->r13, in spm_output_wake_reason()
330 if (wakesta->r12 & WAKE_SRC_SPM_MERGE) { in spm_output_wake_reason()
338 if (wakesta->r12 & (1U << i)) in spm_output_wake_reason()
348 wakesta->timer_out, wakesta->r12, wakesta->r13, in spm_output_wake_reason()
|
| /arm-trusted-firmware-2.8.0/drivers/renesas/common/ddr/ddr_a/ |
| A D | ddr_init_v3m.c | 17 uint32_t i, r2, r5, r6, r7, r12; in init_ddr_v3m_1600() local
273 r12 = (r5 >> 2); in init_ddr_v3m_1600()
274 if (r6 - r12 > 0) { in init_ddr_v3m_1600()
284 mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2); in init_ddr_v3m_1600()
295 (r5 >> 1) + r12) & 0xFF)); in init_ddr_v3m_1600()
|
| A D | ddr_init_d3.c | 26 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1866() local
265 r12 = (r5 >> 0x2); in init_ddr_d3_1866()
267 if (r12 < r6) { in init_ddr_d3_1866()
277 mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); in init_ddr_d3_1866()
288 (r5 >> 1) + r12) & 0xFF)); in init_ddr_d3_1866()
361 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1600() local
611 r12 = (r5 >> 0x2); in init_ddr_d3_1600()
613 if (r12 < r6) { in init_ddr_d3_1600()
623 mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); in init_ddr_d3_1600()
634 (r5 >> 1) + r12) & 0xFF)); in init_ddr_d3_1600()
|
| /arm-trusted-firmware-2.8.0/bl32/sp_min/aarch32/ |
| A D | entrypoint.S | 75 mov r12, r3
124 mov r12, #0
135 mov r3, r12
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spm/constraints/ |
| A D | mt_spm_rc_bus26m.c | 110 wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta, in mt_spm_irq_remain_dump()
132 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) || in do_irqs_delivery()
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spm/constraints/ |
| A D | mt_spm_rc_bus26m.c | 100 wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta, in mt_spm_irq_remain_dump()
122 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) || in do_irqs_delivery()
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/constraints/ |
| A D | mt_spm_rc_bus26m.c | 103 wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta, in mt_spm_irq_remain_dump()
125 if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) || in do_irqs_delivery()
|