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Searched refs:r2 (Results 1 – 25 of 58) sorted by relevance

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/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_helper.S211 str r2, [r1]
214 ands r2, r0, r2
219 ands r2, r0, r2
225 orr r2, r2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN
230 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
231 orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT)
235 bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT)
239 bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT)
244 bic r2, r2, #(GPIO_ALTERNATE_MASK << \
246 orr r2, r2, #(DEBUG_UART_TX_GPIO_ALTERNATE << \
[all …]
/arm-trusted-firmware-2.8.0/lib/libc/aarch32/
A Dmemset.S28 subs r2, r2, #1
40 cmp r2, #16
48 subs r2, r2, #32
53 lsls r2, r2, #28 /* C = r2[4]; N = r2[3]; Z = r2[3:0] */
57 lsls r2, r2, #2 /* C = r2[2]; N = r2[1]; Z = r2[1:0] */
61 lsls r2, r2, #1 /* N = Z = r2[0] */
65 less_16:lsls r2, r2, #29 /* C = r2[3]; N = r2[2]; Z = r2[2:0] */
69 lsls r2, r2, #2 /* C = r2[1]; N = Z = r2[0] */
/arm-trusted-firmware-2.8.0/include/arch/aarch32/
A Dsmccc_macros.S29 stcopr r2, SCR
36 mrs r2, spsr
40 mrs r2, spsr
44 mrs r2, spsr
48 mrs r2, spsr
52 mrs r2, spsr
57 mrs r2, spsr
58 stm r0!, {r2}
171 stcopr r2, SCR
179 msr spsr_fsxc, r2
[all …]
/arm-trusted-firmware-2.8.0/drivers/arm/css/sds/aarch32/
A Dsds_helpers.S23 ldr r2, =SDS_REGION_SIGNATURE
28 cmp r2, r3
40 ldrh r2, [r0]
41 cmp r2, #SDS_AP_CPU_INFO_STRUCT_ID
54 ldr r2, [r0,#4]
56 ubfx r2, r2, #SDS_HEADER_STRUCT_SIZE_SHIFT, #SDS_HEADER_STRUCT_SIZE_WIDTH
58 add r2, r2, #SDS_HEADER_SIZE
59 add r0, r0, r2
/arm-trusted-firmware-2.8.0/lib/xlat_tables_v2/aarch32/
A Denable_mmu.S34 ldr r2, [r0, #(MMU_CFG_TCR << 3)]
35 stcopr r2, TTBCR
39 ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
40 stcopr16 r1, r2, TTBR0_64
44 mov r2, #0
45 stcopr16 r1, r2, TTBR1_64
58 orr r1, r1, r2
91 ldr r2, [r0, #(MMU_CFG_TCR << 3)]
92 stcopr r2, HTCR
97 stcopr16 r1, r2, HTTBR_64
[all …]
/arm-trusted-firmware-2.8.0/drivers/ti/uart/aarch32/
A D16550_console.S47 cmp r2, #0
52 lsl r2, r2, #4
53 udiv r2, r1, r2
55 lsr r2, r2, #8
56 and r2, r2, #0xff /* w2 = DLLM */
62 mov r2, #~UARTLCR_DLAB
63 and r3, r3, r2
153 1: ldr r2, [r1, #UARTLSR]
154 and r2, r2, #(UARTLSR_TEMT | UARTLSR_THRE)
158 str r2, [r1, #UARTTX]
[all …]
/arm-trusted-firmware-2.8.0/lib/extensions/amu/aarch32/
A Damu_helpers.S77 stcopr16 r2, r3, AMEVCNTR00 /* index 0 */
79 stcopr16 r2, r3, AMEVCNTR01 /* index 1 */
216 mov r2, r0
217 lsr r2, r2, #4
218 cmp r2, #0
222 mov r2, r1
223 lsr r2, r2, #16
224 cmp r2, #0
232 adr r2, 1f
234 add r2, r2, r0
[all …]
/arm-trusted-firmware-2.8.0/drivers/renesas/common/ddr/ddr_a/
A Dddr_init_d3.c26 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1866() local
156 r3 = (r2 << 16) + (r2 << 8) + r2; in init_ddr_d3_1866()
157 r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; in init_ddr_d3_1866()
237 r2 = mmio_read_32(DBSC_DBPDRGD_0); in init_ddr_d3_1866()
239 mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); in init_ddr_d3_1866()
242 r2 = mmio_read_32(DBSC_DBPDRGD_0); in init_ddr_d3_1866()
243 mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); in init_ddr_d3_1866()
503 r3 = (r2 << 16) + (r2 << 8) + r2; in init_ddr_d3_1600()
504 r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; in init_ddr_d3_1600()
585 mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); in init_ddr_d3_1600()
[all …]
A Dddr_init_v3m.c17 uint32_t i, r2, r5, r6, r7, r12; in init_ddr_v3m_1600() local
203 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); in init_ddr_v3m_1600()
208 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); in init_ddr_v3m_1600()
210 mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); in init_ddr_v3m_1600()
213 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); in init_ddr_v3m_1600()
215 mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); in init_ddr_v3m_1600()
218 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); in init_ddr_v3m_1600()
220 mmio_write_32(DBSC_DBPDRGD_0, r2 | in init_ddr_v3m_1600()
276 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); in init_ddr_v3m_1600()
289 mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2); in init_ddr_v3m_1600()
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/aarch32/
A Dfvp_helpers.S53 ldcopr r2, MPIDR
55 str r2, [r1, #PSYSR_OFF]
56 ldr r2, [r1, #PSYSR_OFF]
57 ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
58 cmp r2, #WKUP_PPONR
60 cmp r2, #WKUP_GICREQ
134 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
138 mla r1, r2, r3, r1
/arm-trusted-firmware-2.8.0/bl32/sp_min/aarch32/
A Dentrypoint.S74 mov r11, r2
134 mov r2, r11
196 mov r2, sp /* handle */
201 mov r6, r2
213 mov r2, r6
216 ldr r0, [r2, #SMC_CTX_SCR]
231 mov r0, r2
259 mov r2, sp
263 ldr r0, [r2, #SMC_CTX_SCR]
268 push {r2, r3}
[all …]
/arm-trusted-firmware-2.8.0/lib/aarch32/
A Dmisc_helpers.S57 zeroreg1 .req r2 /* Source register filled with 0 */
153 cmp r2, #4
157 subs r2, r2, #4
165 subs r2, r2, #1
234 and r2, lr, r1
240 ldr r2, =__GOT_END__
241 add r2, r2, r0
262 cmp r1, r2
268 ldr r2, =__RELA_END__
269 add r2, r2, r0
[all …]
A Dcache_helpers.S26 dcache_line_size r2, r3
28 sub r3, r2, #1
32 add r0, r0, r2
85 ldcopr r2, CLIDR
86 ubfx r3, r2, \shift, \fw
100 mov r12, r2, LSR r10 // extract cache type bits from clidr
193 ldcopr r2, CLIDR
/arm-trusted-firmware-2.8.0/drivers/arm/pl011/aarch32/
A Dpl011_console.S48 cmp r2, #0
59 softudiv r0,r1,r2,r3
60 mov r2, r0
63 udiv r2, r1, r2
66 lsr r1, r2, #6
70 and r1, r2, #0x3f
144 ldr r2, [r1, #UARTFR]
145 tst r2, #PL011_UARTFR_TXFF
147 mov r2, #0xD
148 str r2, [r1, #UARTDR]
[all …]
/arm-trusted-firmware-2.8.0/drivers/st/uart/aarch32/
A Dstm32_console.S63 cmp r2, #0
76 lsr r3, r2, #1
78 udiv r3, r3, r2
83 lsr r3, r2, #1
85 udiv r3, r3, r2
100 mov r2, #USART_TIMEOUT
102 subs r2, r2, #1
170 ldr r2, [r1, #USART_ISR]
171 tst r2, #USART_ISR_TXE
176 ldr r2, [r1, #USART_ISR]
[all …]
/arm-trusted-firmware-2.8.0/lib/extensions/mtpmu/aarch32/
A Dmtpmu.S67 mov r2, lr
70 bxeq r2 /* FEAT_MTPMU not supported */
90 bx r2
96 bxeq r2 /* No EL2 or EL3 implemented */
104 bx r2
/arm-trusted-firmware-2.8.0/lib/cpus/aarch32/
A Dcpu_helpers.S63 mov r2, #(CPU_MAX_PWR_DWN_OPS - 1)
64 cmp r0, r2
65 movhi r0, r2
69 pop {r2, lr}
79 add r1, r1, r2, lsl #2
133 ldcopr r2, MIDR
137 and r2, r2, r3
148 cmp r1, r2
A Dcortex_a57.S72 mov r2, lr
74 mov lr, r2
116 mov r2, lr
118 mov lr, r2
145 mov r2, lr
154 bx r2
191 mov r2, lr
193 mov lr, r2
220 mov r2, lr
222 mov lr, r2
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/a5ds/aarch32/
A Da5ds_helpers.S28 mov_imm r2, A5DS_HOLD_BASE
31 str r3, [r2, r0]
36 ldr r1, [r2, r0]
117 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
121 mla r1, r2, r3, r1
/arm-trusted-firmware-2.8.0/lib/compiler-rt/builtins/arm/
A Daeabi_ldivmod.S31 movs r0, r2
32 movs r2, r6
38 ldr r2, [sp, #8]
A Daeabi_uldivmod.S31 movs r0, r2
32 movs r2, r6
38 ldr r2, [sp, #8]
/arm-trusted-firmware-2.8.0/drivers/brcm/emmc/
A Demmc_csl_sdcmd.c171 card->csd.mmc.taac = (resp.data.r2.rsp4 >> 8) & 0xff; in sd_cmd9()
172 card->csd.mmc.nsac = resp.data.r2.rsp4 & 0xff; in sd_cmd9()
173 card->csd.mmc.speed = resp.data.r2.rsp3 >> 24; in sd_cmd9()
179 card->csd.mmc.dsr = (resp.data.r2.rsp2 >> 4) & 0x01; in sd_cmd9()
181 ((resp.data.r2.rsp3 & 0x3) << 10) + in sd_cmd9()
182 ((resp.data.r2.rsp2 >> 22) & 0x3ff); in sd_cmd9()
190 ((resp.data.r2.rsp2 & 0x3) << 3) + in sd_cmd9()
191 ((resp.data.r2.rsp1 >> 29) & 0x7); in sd_cmd9()
193 ((resp.data.r2.rsp1 >> 24) & 0x1f); in sd_cmd9()
195 (resp.data.r2.rsp1 >> 23) & 0x1; in sd_cmd9()
[all …]
/arm-trusted-firmware-2.8.0/plat/qemu/common/aarch32/
A Dplat_helpers.S70 mov_imm r2, PLAT_QEMU_HOLD_BASE
74 ldr r1, [r2, r0]
80 str r1, [r2, r0]
111 mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE
/arm-trusted-firmware-2.8.0/include/lib/pmf/aarch32/
A Dpmf_asm_macros.S22 mov r2, #(\_tid * PMF_TS_SIZE)
23 mla r0, r0, r1, r2
/arm-trusted-firmware-2.8.0/lib/locks/exclusive/aarch32/
A Dspinlock.S25 mov r2, #1
30 strexeq r1, r2, [r0]

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