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Searched refs:rcc_base (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/drivers/st/reset/
A Dstm32mp1_reset.c33 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_reset_assert() local
35 mmio_write_32(rcc_base + offset, bitmsk); in stm32mp_reset_assert()
40 while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) { in stm32mp_reset_assert()
54 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_reset_deassert() local
56 mmio_write_32(rcc_base + offset, bitmsk); in stm32mp_reset_deassert()
61 while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) { in stm32mp_reset_deassert()
/arm-trusted-firmware-2.8.0/drivers/st/clk/
A Dstm32mp1_clk.c679 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_secure() local
687 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_mckprot() local
744 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_clk_get_parent() local
798 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_pll_get_fvco() local
853 uintptr_t rcc_base = stm32mp_rcc_base(); in get_clock_rate() local
1054 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_enable() local
1067 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_disable() local
1081 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_is_enabled() local
1233 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_clk_get_rate() local
1969 mmio_write_32(rcc_base + RCC_MPCKDIVR, in stm32mp1_clk_init()
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A Dclk-stm32-core.c916 uintptr_t rcc_base = priv->base; in timer_recalc_rate() local
918 prescaler = mmio_read_32(rcc_base + cfg->apbdiv) & in timer_recalc_rate()
921 timpre = mmio_read_32(rcc_base + cfg->timpre) & in timer_recalc_rate()
A Dclk-stm32mp13.c1020 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_set_hsidiv() local
1021 uintptr_t address = rcc_base + RCC_OCRDYR; in stm32mp1_set_hsidiv()
1023 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, in stm32mp1_set_hsidiv()
/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dbl2_plat_setup.c211 uintptr_t rcc_base; in bl2_el3_plat_arch_setup() local
233 rcc_base = stm32mp_rcc_base(); in bl2_el3_plat_arch_setup()
247 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { in bl2_el3_plat_arch_setup()
248 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
250 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == in bl2_el3_plat_arch_setup()
255 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
260 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); in bl2_el3_plat_arch_setup()
268 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, in bl2_el3_plat_arch_setup()

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