| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/uart/ |
| A D | uart.c | 31 mmio_write_32(UART_EFR(base), uart->registers.efr); in mt_uart_restore()
32 mmio_write_32(UART_LCR(base), uart->registers.lcr); in mt_uart_restore()
33 mmio_write_32(UART_FCR(base), uart->registers.fcr); in mt_uart_restore()
40 uart->registers.lcr | UART_LCR_DLAB); in mt_uart_restore()
41 mmio_write_32(UART_DLL(base), uart->registers.dll); in mt_uart_restore()
42 mmio_write_32(UART_DLH(base), uart->registers.dlh); in mt_uart_restore()
45 uart->registers.sample_count); in mt_uart_restore()
47 uart->registers.sample_point); in mt_uart_restore()
82 uart->registers.lcr | UART_LCR_DLAB); in mt_uart_save()
86 uart->registers.sample_count = mmio_read_32( in mt_uart_save()
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| A D | uart.h | 91 struct mt_uart_register registers; member
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 5 | Title | Not saving x0 to x3 registers can leak information from one |
28 into the firmware. However, for an SMC exception, the general purpose registers
32 caller in registers ``x0`` to ``x3``. In TF-A, these return values are written
37 called. It restores the values of all general purpose registers taken from the
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
45 * This function restores all general purpose registers except x30 from the
75 SMCs it would need to be aware of which return registers contain valid data, so
76 it can sanitise any unused return registers. On the other hand, mitigating this
78 information is leaked through registers ``x0`` to ``x3``, by preserving the
82 ``SP_MIN`` already saves all general purpose registers - including ``r0`` to
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| A D | security-advisory-tfv-5.rst | 38 to the list of saved/restored registers both when entering EL3 and also
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| A D | security-advisory-tfv-2.rst | 31 by saving and restoring the appropriate debug registers), this may allow a
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | context_mgmt_rework.rst | 50 SPM in S-EL2, there is some code initializing S-EL1 registers which is
75 function which takes care of saving and restoring all the registers for
77 CPU features to select registers to save and restore. It also assumes that
81 registers which can be controlled by the dispatcher.
85 within the CPU Context for each set of registers will be controlled by a
109 helpers to initialize registers corresponding to certain features but
135 a collection of EL3 and some other lower EL registers. The save and restore
161 own copy of PAuth registers which needs to be restored on every
171 on EL3 Exit and possibly only some registers in `root_exc_context`
183 registers easily for its own purposes and also have a fixed EL3 sysreg setting
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 40 ``cm_get_context()`` , then programming the registers in the non-secure
43 FIQs to the secure world, the values of the registers can be modified prior
71 X0 (AArch64) and restore other registers as per `SMCCC`_.
77 registers according to `PSCI specification`_ during cold/warm boot.
81 system registers which do not require coordination with the EL3 Runtime
88 registers need to be saved and restored according to `SMCCC`_. In AArch64,
102 #. Values for certain system registers like SCR and SCTLR cannot be
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
141 data and program the registers as it will done implicitly as part of
148 modify any of the system registers affecting the secure world and instead
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| A D | build-options.rst | 162 the AArch32 system registers to be included when saving and restoring the
174 registers to be included when saving and restoring the CPU context. Default
178 registers in cpu context. This must be enabled, if the platform wants to use
184 registers to be saved/restored when entering/exiting an EL2 execution
189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
363 access their own MPAM registers without trapping into EL3. This option
405 registers so are enabled together. Using this option without
429 which are aliased by the SIMD and FP registers. The build option is not
688 wants the timer registers to be saved and restored.
1001 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
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| /arm-trusted-firmware-2.8.0/tools/marvell/doimage/secure/ |
| A D | sec_img_7K.cfg | 26 # SecureBootControl and EfuseBurnControl registers array
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| A D | sec_img_8K.cfg | 26 # SecureBootControl and EfuseBurnControl registers array
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | rmm-el3-comms-spec.rst | 488 specific to each world and will save and restore the registers
494 #. General purpose registers (x0-x30) and ``sp_el0``, ``sp_el2`` stack pointers
495 …atures by EL3. These include system registers with the ``_EL2`` prefix. The EL2 physical and virtu…
503 EL3 will not save some registers as mentioned in the below list. It is the
507 #. FP/SIMD registers
508 #. SVE registers
509 #. SME registers
510 #. EL1/0 registers
512 It is the responsibility of EL3 that any other registers other than the ones mentioned above
517 to clear SVE registers if they have been used in Realm World. The same applies
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| A D | arm-sip-service.rst | 65 switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
72 entered for the first time, following power on. This means CPU registers that
74 registers should not be expected to hold their values before the call was made.
87 Instead, execution starts at the supplied entry point, with the CPU registers 0
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| A D | sdei.rst | 33 registers a handler for that event [3], enables the event [5], and unmasks all
233 As part of initialisation, the SDEI client registers a handler for a platform
310 registers except ``x0`` to ``x17``. This has significance if event handler is
332 return to the handler, the epilogue never gets executed, and registers ``x29``
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| A D | ras.rst | 35 error record registers from Non-secure.
55 nodes contain one or more error records, which are registers through which the
59 memory-mapped registers.
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| /arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst | 15 - **0x3** = PCIe registers
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | trusted-board-boot-build.rst | 50 root-key storage registers present in the platform. On Juno, these
51 registers are read-only. On FVP Base and Cortex models, the registers
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| A D | reset-design.rst | 145 that can be passed in registers by previous boot stages. Instead, the platform
152 receive parameters in registers depending on their actual boot sequence. On
154 set ``RESET_TO_BL31_WITH_PARAMS`` to avoid the input registers from being
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| /arm-trusted-firmware-2.8.0/docs/perf/ |
| A D | performance-monitoring-unit.rst | 50 ``PMCR`` registers. These can be accessed at all privilege levels.
147 regardless of how the other PMU system registers or bit fields are
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/ |
| A D | arm-build-options.rst | 14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
27 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
29 to have a Linux kernel image as BL33 by preparing the registers to these
60 registers.
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 30 - ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
34 code (only architectural system registers, and no errata).
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| /arm-trusted-firmware-2.8.0/docs/components/fconf/ |
| A D | amu-bindings.rst | 38 registers of one or more |AMUs|, and may be shared by multiple cores.
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| /arm-trusted-firmware-2.8.0/plat/renesas/common/ |
| A D | common.mk | 80 PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
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| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | threat_model.rst | 72 | | to registers and memory of TF-A. |
86 | | interrupts and registers. |
472 | | information of the CPU state, current registers |
544 | | modify TF-A registers and memory allowing the |
722 | Mitigations | Save and restore registers when switching contexts. |
728 | | additional registers such as floating-point |
729 | | registers. These should be enabled if required. |
838 | | | Non-secure software can configure PMU registers |
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| /arm-trusted-firmware-2.8.0/docs/plat/nxp/ |
| A D | nxp-ls-fuse-prov.rst | 20 - SFP registers to be written to:
92 - At U-Boot prompt, verify that SNVS registers for OTPMK are correctly written:
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| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | security.rst | 69 | |TFV-8| | Not saving x0 to x3 registers can leak information from one |
|