| /arm-trusted-firmware-2.8.0/plat/brcm/board/common/ |
| A D | platform_common.c | 70 void __dead2 plat_soft_reset(uint32_t reset) in plat_soft_reset() argument
72 if (reset == SOFT_RESET_L3) { in plat_soft_reset()
73 mmio_setbits_32(CRMU_IHOST_SW_PERSISTENT_REG1, reset); in plat_soft_reset()
78 if (reset != SOFT_SYS_RESET_L1) in plat_soft_reset()
79 reset = SOFT_PWR_UP_RESET_L0; in plat_soft_reset()
81 if (reset == SOFT_PWR_UP_RESET_L0) in plat_soft_reset()
84 if (reset == SOFT_SYS_RESET_L1) in plat_soft_reset()
89 mmio_clrbits_32(CRMU_SOFT_RESET_CTRL, 1 << reset); in plat_soft_reset()
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| A D | cmn_plat_util.h | 41 void plat_soft_reset(uint32_t reset);
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | reset-design.rst | 13 General reset code flow
19 |Default reset code flow|
32 Programmable CPU reset address
40 If the reset vector address (reflected in the reset vector base address register
45 |Reset code flow with programmable reset address|
67 |Reset code flow with single CPU released out of reset|
77 Programmable CPU reset address, Cold boot on a single CPU
81 a programmable CPU reset address and which release a single CPU out of reset.
85 |Reset code flow with programmable reset address and single CPU released out of reset|
91 Using BL31 entrypoint as the reset address
[all …]
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| A D | index.rst | 14 reset-design
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spm/ |
| A D | mt_spm.c | 47 .reset = spm_reset_rc_bus26m,
55 .reset = spm_reset_rc_syspll,
63 .reset = spm_reset_rc_dram,
71 .reset = spm_reset_rc_cpu_buck_ldo,
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spm/ |
| A D | mt_spm.c | 52 .reset = spm_reset_rc_bus26m,
60 .reset = spm_reset_rc_syspll,
68 .reset = spm_reset_rc_dram,
76 .reset = spm_reset_rc_cpu_buck_ldo,
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/ |
| A D | mt_spm.c | 55 .reset = spm_reset_rc_bus26m,
63 .reset = spm_reset_rc_syspll,
71 .reset = spm_reset_rc_dram,
80 .reset = spm_reset_rc_cpu_buck_ldo,
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| /arm-trusted-firmware-2.8.0/plat/st/common/ |
| A D | stm32mp_common.c | 151 static void reset_uart(uint32_t reset) in reset_uart() argument
155 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); in reset_uart()
162 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); in reset_uart()
206 (dt_uart_info.reset < 0)) { in stm32mp_uart_console_setup()
227 reset_uart((uint32_t)dt_uart_info.reset); in stm32mp_uart_console_setup()
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| A D | stm32mp_dt.c | 159 info->reset = (int)fdt32_to_cpu(*cuint); in dt_fill_device_info()
161 info->reset = -1; in dt_fill_device_info()
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| /arm-trusted-firmware-2.8.0/plat/allwinner/common/ |
| A D | arisc_off.S | 16 # This routine is meant to be called directly from arisc reset (put the
17 # start address in the reset vector), to be actually triggered by that
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
76 reset: l.sw 0x1c00(r13),r0 # pull down our own reset line label
78 l.j reset # just in case ....
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| /arm-trusted-firmware-2.8.0/plat/xilinx/versal/pm_service/ |
| A D | pm_svc_main.h | 17 int32_t pm_register_sgi(uint32_t sgi_num, uint32_t reset);
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| A D | pm_svc_main.c | 88 int32_t pm_register_sgi(uint32_t sgi_num, uint32_t reset) in pm_register_sgi() argument
90 if (reset == 1U) { in pm_register_sgi()
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| /arm-trusted-firmware-2.8.0/plat/mediatek/common/lpm/ |
| A D | mt_lp_rm.c | 50 if ((rc == NULL) || (rc->reset == NULL)) { in mt_lp_rm_reset_constraint()
54 return rc->reset(cpuid, stateid); in mt_lp_rm_reset_constraint()
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| A D | mt_lp_rm.h | 26 int (*reset)(unsigned int cpu, int stateid); member
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| /arm-trusted-firmware-2.8.0/drivers/st/crypto/ |
| A D | stm32_rng.c | 250 if (dt_rng.reset >= 0) { in stm32_rng_init()
253 ret = stm32mp_reset_assert((unsigned long)dt_rng.reset, in stm32_rng_init()
261 ret = stm32mp_reset_deassert((unsigned long)dt_rng.reset, in stm32_rng_init()
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| A D | stm32_hash.c | 349 if (hash_info.reset >= 0) { in stm32_hash_register()
350 uint32_t id = (uint32_t)hash_info.reset; in stm32_hash_register()
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| /arm-trusted-firmware-2.8.0/plat/st/common/include/ |
| A D | stm32mp_dt.h | 22 int32_t reset; member
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-5.rst | 41 Furthermore, ``PMCR_EL0.DP`` has an architecturally ``UNKNOWN`` reset value.
44 bits with an architecturally UNKNOWN reset value should be initialized to
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| A D | security-advisory-tfv-7.rst | 55 initialization, following every PE reset. No mechanism is provided to disable
76 initialization, following every PE reset. In addition, this approach implements
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | fvp-foundation-motherboard.dtsi | 150 * reset@0 {
151 * compatible = "arm,vexpress-reset";
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| A D | rtsm_ve-motherboard.dtsi | 55 reset {
56 compatible = "arm,vexpress-reset";
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| /arm-trusted-firmware-2.8.0/docs/plat/nxp/ |
| A D | nxp-layerscape.rst | 360 -- Then reset to alternate bank to boot up ATF.
372 cpld reset altbank;
394 -- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source.
406 cpld reset <sd or emmc>;
418 -- Then reset to alternate bank to boot up ATF.
424 cpld reset altbank;
436 -- Then reset to nand flash to boot up ATF.
442 cpld reset nand;
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/fvp/ |
| A D | index.rst | 358 Running on the Foundation FVP with reset to BL1 entrypoint
395 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
419 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
447 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
465 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
484 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
519 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
532 reset vector for each core.
540 Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
581 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
[all …]
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/corstone1000/ |
| A D | index.rst | 20 Then, the application processor is released from reset and starts by
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| /arm-trusted-firmware-2.8.0/drivers/renesas/common/emmc/ |
| A D | emmc_cmd.c | 43 goto reset; in emmc_softreset()
58 reset: in emmc_softreset()
|