/arm-trusted-firmware-2.8.0/plat/amlogic/common/ |
A D | aml_scpi.c | 46 uint32_t response = aml_mhu_secure_message_wait(); in aml_scpi_secure_message_receive() local 48 size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; in aml_scpi_secure_message_receive() 50 response &= ~(SIZE_MASK << SIZE_SHIFT); in aml_scpi_secure_message_receive() 58 return response; in aml_scpi_secure_message_receive() 79 uint32_t *response; in aml_scpi_sys_power_state() local 88 return *response; in aml_scpi_sys_power_state() 110 uint32_t *response; in aml_scpi_efuse_read() local 127 if (*response != 0) in aml_scpi_efuse_read() 128 memcpy(dst, response + 1, *response); in aml_scpi_efuse_read() 130 return *response; in aml_scpi_efuse_read() [all …]
|
/arm-trusted-firmware-2.8.0/drivers/arm/css/scp/ |
A D | css_pm_scpi.c | 122 uint32_t response; in css_scp_sys_shutdown() local 131 response = scpi_sys_power_state(scpi_system_shutdown); in css_scp_sys_shutdown() 133 if (response != SCP_OK) { in css_scp_sys_shutdown() 134 ERROR("CSS System Off: SCP error %u.\n", response); in css_scp_sys_shutdown() 147 uint32_t response; in css_scp_sys_reboot() local 156 response = scpi_sys_power_state(scpi_system_reboot); in css_scp_sys_reboot() 158 if (response != SCP_OK) { in css_scp_sys_reboot() 159 ERROR("CSS System Reset: SCP error %u.\n", response); in css_scp_sys_reboot()
|
A D | css_bom_bootloader.c | 106 uint32_t response; in css_scp_boot_image_xfer() local 159 response = scp_boot_message_wait(sizeof(response)); in css_scp_boot_image_xfer() 162 if (response != 0) { in css_scp_boot_image_xfer() 163 ERROR("SCP BOOT_CMD_INFO returned error %u\n", response); in css_scp_boot_image_xfer() 178 response = scp_boot_message_wait(sizeof(response)); in css_scp_boot_image_xfer() 181 if (response != 0) { in css_scp_boot_image_xfer() 182 ERROR("SCP BOOT_CMD_DATA returned error %u\n", response); in css_scp_boot_image_xfer()
|
/arm-trusted-firmware-2.8.0/plat/brcm/common/ |
A D | brcm_mhu.c | 61 uint32_t response, iter = 1000000; in mhu_secure_message_send() local 74 response = mmio_read_32(CRMU_MAIL_BOX0); in mhu_secure_message_send() 75 if ((response & ~MCU_IPC_CMD_REPLY_MASK) == in mhu_secure_message_send() 89 uint32_t response, iter = 1000000; in mhu_secure_message_wait() local 92 response = mmio_read_32(PLAT_BRCM_MHU_BASE + SCP_INTR_S_STAT); in mhu_secure_message_wait() 93 if (!response) in mhu_secure_message_wait() 100 return response; in mhu_secure_message_wait()
|
A D | brcm_scpi.c | 182 scpi_cmd_t response; in scpi_get_brcm_power_state() local 205 scpi_secure_message_receive(&response); in scpi_get_brcm_power_state() 207 if (response.status != SCP_OK) in scpi_get_brcm_power_state() 211 if (!CHECK_RESPONSE(response, cluster)) in scpi_get_brcm_power_state()
|
/arm-trusted-firmware-2.8.0/plat/socionext/synquacer/drivers/scpi/ |
A D | sq_scpi.c | 153 scpi_cmd_t response; in scpi_sys_power_state() local 168 scpi_secure_message_receive(&response); in scpi_sys_power_state() 172 return response.status; in scpi_sys_power_state() 181 } response; in scpi_get_draminfo() local 211 memcpy(&response, (void *)SCPI_SHARED_MEM_SCP_TO_AP, sizeof(response)); in scpi_get_draminfo() 215 if (response.cmd.status == SCP_OK) in scpi_get_draminfo() 216 *info = response.info; in scpi_get_draminfo() 218 return response.cmd.status; in scpi_get_draminfo()
|
/arm-trusted-firmware-2.8.0/drivers/arm/css/scmi/vendor/ |
A D | scmi_sq.c | 31 struct dram_info_resp response; in scmi_get_draminfo() local 55 memcpy(&response, (void *)mbx_mem->payload, sizeof(response)); in scmi_get_draminfo() 59 *info = response.info; in scmi_get_draminfo()
|
/arm-trusted-firmware-2.8.0/drivers/renesas/common/emmc/ |
A D | emmc_utility.c | 146 mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data; in emmc_make_nontrans_cmd() 150 mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; in emmc_make_nontrans_cmd() 154 mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; in emmc_make_nontrans_cmd() 157 mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data; in emmc_make_nontrans_cmd() 161 mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; in emmc_make_nontrans_cmd() 164 mmc_drv_obj.response = &mmc_drv_obj.r4_resp; in emmc_make_nontrans_cmd() 167 mmc_drv_obj.response = &mmc_drv_obj.r5_resp; in emmc_make_nontrans_cmd() 170 mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data; in emmc_make_nontrans_cmd() 213 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_send_idle_cmd()
|
A D | emmc_cmd.c | 70 static void emmc_read_response(uint32_t *response) in emmc_read_response() argument 74 if (response == NULL) in emmc_read_response() 79 *response = GETR_32(SD_RSP10); /* [39:8] */ in emmc_read_response() 84 p = (uint8_t *) (response); in emmc_read_response() 101 if (response == NULL) in emmc_response_check() 111 (EMMC_R1_STATE) ((*response & EMMC_R1_STATE_MASK) >> in emmc_response_check() 113 if ((*response & error_mask) != 0) { in emmc_response_check() 114 if ((0x80 & *response) != 0) { in emmc_response_check() 123 if ((*response & EMMC_R4_STATUS) != 0) in emmc_response_check() 207 if (response == NULL) { in emmc_exec_cmd() [all …]
|
A D | emmc_mount.c | 94 emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_card_init() 124 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_card_init() 132 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_card_init() 141 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_card_init() 156 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_card_init() 191 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_card_init() 205 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_card_init() 248 emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_high_speed() 336 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_bus_width() 361 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_bus_width() [all …]
|
A D | emmc_read.c | 36 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_multiple_block_read() 50 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_multiple_block_read() 57 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); in emmc_multiple_block_read()
|
A D | emmc_def.h | 62 EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response);
|
/arm-trusted-firmware-2.8.0/drivers/arm/css/scpi/ |
A D | css_scpi.c | 187 scpi_cmd_t response; in scpi_get_css_power_state() local 219 if (scpi_secure_message_receive(&response) != 0) in scpi_get_css_power_state() 222 if (response.status != SCP_OK) in scpi_get_css_power_state() 226 if (!CHECK_RESPONSE(response, cluster)) in scpi_get_css_power_state() 250 scpi_cmd_t response; in scpi_sys_power_state() local 266 if (scpi_secure_message_receive(&response) != 0) in scpi_sys_power_state() 267 response.status = SCP_E_TIMEOUT; in scpi_sys_power_state() 271 return response.status; in scpi_sys_power_state()
|
/arm-trusted-firmware-2.8.0/plat/socionext/synquacer/drivers/mhu/ |
A D | sq_mhu.c | 61 uint32_t response; in mhu_secure_message_wait() local 64 while (!(response = mmio_read_32(PLAT_SQ_MHU_BASE + SCP_INTR_S_STAT))) in mhu_secure_message_wait() 67 return response; in mhu_secure_message_wait()
|
/arm-trusted-firmware-2.8.0/drivers/arm/css/mhu/ |
A D | css_mhu.c | 65 uint32_t response; in mhu_secure_message_wait() local 66 while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) in mhu_secure_message_wait() 69 return response; in mhu_secure_message_wait()
|
/arm-trusted-firmware-2.8.0/drivers/nxp/sd/ |
A D | sd_mmc.c | 320 if (response != NULL) { in esdhc_wait_response() 328 INFO("Resp R1 = %x\n", response[0]); in esdhc_wait_response() 329 INFO("R2 = %x\n", response[1]); in esdhc_wait_response() 330 INFO("R3 = %x\n", response[2]); in esdhc_wait_response() 331 INFO("R4 = %x\n", response[3]); in esdhc_wait_response() 357 uint32_t response[4]; in mmc_switch_to_high_frquency() local 393 if ((response[0] & SWITCH_ERROR) != 0) { in mmc_switch_to_high_frquency() 764 uint32_t response[4]; in sd_switch_to_high_freq() local 876 uint32_t response[4]; in change_state_to_transfer_state() local 930 uint32_t response[4]; in get_cid_rca_csd() local [all …]
|
/arm-trusted-firmware-2.8.0/plat/socionext/synquacer/ |
A D | sq_psci.c | 153 uint32_t response; in sq_system_reset() 156 response = scpi_sys_power_state(scpi_system_reboot); in sq_system_reset() 158 if (response != SCP_OK) { in sq_system_reset() 159 ERROR("SQ System Reset: SCP error %u.\n", response); in sq_system_reset()
|
/arm-trusted-firmware-2.8.0/plat/intel/soc/common/soc/ |
A D | socfpga_mailbox.c | 161 if (iterate_resp(ret_resp_len, response, resp_len) in mailbox_read_response() 177 uint32_t *response, unsigned int *resp_len, in mailbox_read_response_async() argument 244 memcpy((uint8_t *) response, in mailbox_read_response_async() 323 if (iterate_resp(ret_resp_len, response, resp_len) in mailbox_poll_response() 415 unsigned int len, uint32_t urgent, uint32_t *response, in mailbox_send_cmd() argument 582 uint32_t res, response[6]; in intel_mailbox_get_config_status() local 583 unsigned int resp_len = ARRAY_SIZE(response); in intel_mailbox_get_config_status() 586 response, &resp_len); in intel_mailbox_get_config_status() 592 res = response[RECONFIG_STATUS_STATE]; in intel_mailbox_get_config_status() 597 res = response[RECONFIG_STATUS_PIN_STATUS]; in intel_mailbox_get_config_status() [all …]
|
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/ |
A D | hikey_private.h | 60 int hikey_get_partition_size(const char *arg, int left, char *response); 61 int hikey_get_partition_type(const char *arg, int left, char *response);
|
/arm-trusted-firmware-2.8.0/drivers/brcm/ |
A D | spi_sf.c | 49 int spi_flash_cmd(uint8_t cmd, void *response, size_t len) in spi_flash_cmd() argument 51 return spi_flash_cmd_read(&cmd, CMD_LEN1, response, len); in spi_flash_cmd()
|
/arm-trusted-firmware-2.8.0/plat/intel/soc/common/include/ |
A D | socfpga_mailbox.h | 213 unsigned int len, uint32_t urgent, uint32_t *response, 219 int mailbox_read_response(uint32_t *job_id, uint32_t *response, 222 uint32_t *response, unsigned int *resp_len,
|
/arm-trusted-firmware-2.8.0/include/drivers/brcm/ |
A D | sf.h | 87 int spi_flash_cmd(uint8_t cmd, void *response, size_t len);
|
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/fdts/ |
A D | optee_sp_manifest.dts | 28 messaging-method = <0x3>; /* Direct request/response supported. */
|
/arm-trusted-firmware-2.8.0/docs/threat_model/ |
A D | threat_model_el3_spm.rst | 59 | | LSP can send direct response SP1 or NWd through SPMC. | 142 | | FF-A ID in a direct request/response invocation.** | 168 | | request/response interfaces such an endpoint cannot| 172 | | Also enforces check for direct response being sent | 180 | | FF-A ID in a direct request/response invocation.** | 212 | | request/response filtering. | 411 | | response.** | 414 | | message by a direct message response with | 416 | | (e.g. partition message response outside of | 444 | | to be revealed through a direct message response. |
|
/arm-trusted-firmware-2.8.0/plat/intel/soc/common/ |
A D | socfpga_sip_svc.c | 214 uint32_t response[3]; in intel_fpga_config_start() local 217 unsigned int resp_len = ARRAY_SIZE(response); in intel_fpga_config_start() 237 CMD_CASUAL, response, &resp_len); in intel_fpga_config_start() 245 max_blocks = response[0]; in intel_fpga_config_start() 246 bytes_per_block = response[1]; in intel_fpga_config_start() 520 unsigned int len, uint32_t urgent, uint64_t response, in intel_mbox_send_cmd() argument 532 (uint32_t *) response, &resp_len); in intel_mbox_send_cmd() 542 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); in intel_mbox_send_cmd()
|