Searched refs:restore (Results 1 – 16 of 16) sorted by relevance
72 (4) **Allow more flexibility for Dispatchers to select feature set to save and restore**74 The current functions for EL2 CPU context save and restore is a single77 CPU features to select registers to save and restore. It also assumes that80 world. The framework should cater for selective save and restore of CPU84 save and restore routine corresponding to Arch feature. The memory allocation126 some functionalities in EL3. The current sequence for context save and restore135 a collection of EL3 and some other lower EL registers. The save and restore139 Note2: The EL1 context save and restore can possibly be removed when switching168 sysregs (`root_exc_context`) used by EL3. The save and restore
10 the |AMU| prior to its exit from EL3, and will save and restore architected
14 invoked by RMM as well as the register save-restore convention when handling an208 restore convention between EL3 and RMM as part of RMI call handling. It is484 RMM-EL3 world switch register save restore convention488 specific to each world and will save and restore the registers
288 - The caller must be prepared for the SDEI dispatcher to restore the Non-secure
156 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
173 static void ble_plat_mmap_config(int restore) in ble_plat_mmap_config() argument175 if (restore == MMAP_RESTORE_SAVED) { in ble_plat_mmap_config()
35 Since TF-A does not save and restore ``PMCR_EL0`` when switching between the
27 restore it before returning into the lower exception level software that called
79 it needs to save/restore. Although the ``BPIALL`` instruction is not effective
167 - ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore260 to EL3 context save/restore operations. This flag can take the values 0 to 2,273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an286 Physical Offset register) during EL2 to EL3 context save/restore operations.293 Read Trap Register) during EL2 to EL3 context save/restore operations.300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a346 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory685 - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register686 contents upon world switch. It can take either 0 (don't save and restore) or687 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it[all …]
71 X0 (AArch64) and restore other registers as per `SMCCC`_.449 Typical bookkeeping during PSCI power management calls include save/restore
2856 setup required to restore the saved state for this CPU to resume execution
722 | Mitigations | Save and restore registers when switching contexts. |727 | | Build options are also provided to save/restore |
3354 static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) in wdqdm_cp() argument3372 if (restore) in wdqdm_cp()
722 security state. It must then restore the system register context of the743 restore the non-secure context and arrange for entry into the non-secure state
986 …- enable fpregs context save and restore ([18fa43f](https://review.trustedfirmware.org/plugins/git…1261 …- add gic save and restore calls ([b40a467](https://review.trustedfirmware.org/plugins/gitiles/TF-…3134 - UART save and restore3622 - Fixed the EL2 context save/restore routine by removing EL2 generic timer3990 - Fixed runtime instability caused by improper register save/restore routine4086 - Build option to support EL2 context save and restore in the secure world4089 that the support is compliant, but the SVE registers save/restore will be4396 save restore routines4629 IPL and Secure Monitor Rev2.0.4, Change to restore timer counter value at5530 - Added helpers to save / restore the GICv3 context, specifically the[all …]
Completed in 39 milliseconds