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Searched refs:sdram_mode (Results 1 – 12 of 12) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046ardb/
A Dddr_init.c41 .sdram_mode[8] = U(0x500),
42 .sdram_mode[2] = U(0x10631),
44 .sdram_mode[10] = U(0x400),
46 .sdram_mode[4] = U(0x10631),
48 .sdram_mode[12] = U(0x400),
52 .sdram_mode[14] = U(0x400),
86 .sdram_mode[8] = U(0x500),
132 .sdram_mode[1] = U(0x0),
136 .sdram_mode[3] = U(0x0),
140 .sdram_mode[5] = U(0x0),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160aqds/
A Dddr_init.c48 .sdram_mode[2] = U(0x00),
49 .sdram_mode[3] = U(0x00),
50 .sdram_mode[4] = U(0x00),
51 .sdram_mode[5] = U(0x00),
52 .sdram_mode[6] = U(0x00),
53 .sdram_mode[7] = U(0x00),
56 .sdram_mode[10] = U(0x00),
57 .sdram_mode[11] = U(0x00),
58 .sdram_mode[12] = U(0x00),
59 .sdram_mode[13] = U(0x00),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2162aqds/
A Dddr_init.c48 .sdram_mode[2] = U(0x00),
49 .sdram_mode[3] = U(0x00),
50 .sdram_mode[4] = U(0x00),
51 .sdram_mode[5] = U(0x00),
52 .sdram_mode[6] = U(0x00),
53 .sdram_mode[7] = U(0x00),
56 .sdram_mode[10] = U(0x00),
57 .sdram_mode[11] = U(0x00),
58 .sdram_mode[12] = U(0x00),
59 .sdram_mode[13] = U(0x00),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ls1043ardb/
A Dddr_init.c30 .sdram_mode[0] = U(0x3010210),
31 .sdram_mode[9] = U(0x4000000),
32 .sdram_mode[8] = U(0x500),
33 .sdram_mode[2] = U(0x10210),
34 .sdram_mode[10] = U(0x400),
35 .sdram_mode[11] = U(0x4000000),
36 .sdram_mode[4] = U(0x10210),
37 .sdram_mode[12] = U(0x400),
38 .sdram_mode[13] = U(0x4000000),
39 .sdram_mode[6] = U(0x10210),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ls1028ardb/
A Dddr_init.c28 .sdram_mode[0] = U(0x3010210),
29 .sdram_mode[9] = U(0x4000000),
30 .sdram_mode[8] = U(0x500),
31 .sdram_mode[2] = U(0x10210),
32 .sdram_mode[10] = U(0x400),
33 .sdram_mode[11] = U(0x4000000),
34 .sdram_mode[4] = U(0x10210),
35 .sdram_mode[12] = U(0x400),
36 .sdram_mode[13] = U(0x4000000),
37 .sdram_mode[6] = U(0x10210),
[all …]
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/
A Dregs.c633 regs->sdram_mode[0] = (((esdmode & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
635 debug("sdram_mode[0] = 0x%x\n", regs->sdram_mode[0]); in cal_ddr_sdram_mode()
673 regs->sdram_mode[1] = ((esdmode2 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
675 debug("sdram_mode[1] = 0x%x\n", regs->sdram_mode[1]); in cal_ddr_sdram_mode()
684 regs->sdram_mode[9] = ((esdmode6 & 0xffff) << 16) | in cal_ddr_sdram_mode()
686 debug("sdram_mode[9] = 0x%x\n", regs->sdram_mode[9]); in cal_ddr_sdram_mode()
756 regs->sdram_mode[8] = ((esdmode4 & 0xffff) << 16) | in cal_ddr_sdram_mode()
761 regs->sdram_mode[2] = (((esdmode & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
763 regs->sdram_mode[3] = ((esdmode2 & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
775 regs->sdram_mode[4] = (((esdmode & 0xFFFF) << 16) | in cal_ddr_sdram_mode()
[all …]
A Dddrc.c243 ddr_out32(&ddr->sdram_mode, regs->sdram_mode[0]); in ddrc_set_regs()
244 ddr_out32(&ddr->sdram_mode_2, regs->sdram_mode[1]); in ddrc_set_regs()
245 ddr_out32(&ddr->sdram_mode_3, regs->sdram_mode[2]); in ddrc_set_regs()
246 ddr_out32(&ddr->sdram_mode_4, regs->sdram_mode[3]); in ddrc_set_regs()
247 ddr_out32(&ddr->sdram_mode_5, regs->sdram_mode[4]); in ddrc_set_regs()
248 ddr_out32(&ddr->sdram_mode_6, regs->sdram_mode[5]); in ddrc_set_regs()
249 ddr_out32(&ddr->sdram_mode_7, regs->sdram_mode[6]); in ddrc_set_regs()
250 ddr_out32(&ddr->sdram_mode_8, regs->sdram_mode[7]); in ddrc_set_regs()
251 ddr_out32(&ddr->sdram_mode_9, regs->sdram_mode[8]); in ddrc_set_regs()
252 ddr_out32(&ddr->sdram_mode_10, regs->sdram_mode[9]); in ddrc_set_regs()
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046afrwy/
A Dddr_init.c39 .sdram_mode[0] = U(0x01010210),
40 .sdram_mode[1] = U(0x0),
41 .sdram_mode[8] = U(0x00000500),
42 .sdram_mode[9] = U(0x04000000),
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160ardb/
A Dddr_init.c40 .sdram_mode[0] = U(0x6010210),
41 .sdram_mode[8] = U(0x500),
42 .sdram_mode[9] = U(0x4240000),
/arm-trusted-firmware-2.8.0/include/drivers/nxp/ddr/
A Dimmap.h36 unsigned int sdram_mode; /* SDRAM Mode Configuration */ member
A Dddr.h58 unsigned int sdram_mode[16]; member
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/phy-gen2/
A Dphy.c2507 input.mr[0] = regs->sdram_mode[0] & U(0xffff); in compute_ddr_phy()
2508 input.mr[1] = regs->sdram_mode[0] >> 16U; in compute_ddr_phy()
2509 input.mr[2] = regs->sdram_mode[1] >> 16U; in compute_ddr_phy()
2510 input.mr[3] = regs->sdram_mode[1] & U(0xffff); in compute_ddr_phy()
2511 input.mr[4] = regs->sdram_mode[8] >> 16U; in compute_ddr_phy()
2512 input.mr[5] = regs->sdram_mode[8] & U(0xffff); in compute_ddr_phy()
2513 input.mr[6] = regs->sdram_mode[9] >> 16U; in compute_ddr_phy()

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