| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | stm32mp135f-dk.dts | 17 compatible = "st,stm32mp135f-dk", "st,stm32mp135";
55 st,non-secure-otp;
118 st,mask-reset;
188 st,clksrc = <
206 st,clkdiv = <
218 st,pll_vco {
244 pll1:st,pll@0 {
257 pll2:st,pll@1 {
270 pll3:st,pll@2 {
283 pll4:st,pll@3 {
[all …]
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| A D | stm32mp15-ddr.dtsi | 7 st,mem-name = DDR_MEM_NAME;
8 st,mem-speed = <DDR_MEM_SPEED>;
9 st,mem-size = <DDR_MEM_SIZE>;
11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
86 st,phy-reg = <
100 st,phy-timing = <
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| A D | stm32mp157c-ed1.dts | 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
36 st,non-secure-otp;
41 st,digbypass;
109 st,mask-reset;
204 st,clksrc = <
216 st,clkdiv = <
230 st,pkcs = <
312 st,sig-dir;
313 st,neg-edge;
314 st,use-ckin;
[all …]
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| A D | stm32mp151.dtsi | 209 st,tzcr = <&rcc 0x0 0x1>;
257 st,irq-number = <6>;
495 st,non-secure-otp;
552 st,bank-name = "GPIOA";
563 st,bank-name = "GPIOB";
574 st,bank-name = "GPIOC";
585 st,bank-name = "GPIOD";
596 st,bank-name = "GPIOE";
607 st,bank-name = "GPIOF";
618 st,bank-name = "GPIOG";
[all …]
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| A D | stm32mp157a-avenger96.dts | 90 st,mask-reset;
174 st,clksrc = <
186 st,clkdiv = <
200 st,pkcs = <
239 pll1: st,pll@0 {
247 pll2: st,pll@1 {
255 pll3: st,pll@2 {
263 pll4: st,pll@3 {
281 st,sig-dir;
282 st,neg-edge;
[all …]
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| A D | stm32mp131.dtsi | 82 compatible = "st,stm32h7-uart";
456 st,non-secure-otp;
482 st,bank-name = "GPIOA";
494 st,bank-name = "GPIOB";
506 st,bank-name = "GPIOC";
518 st,bank-name = "GPIOD";
530 st,bank-name = "GPIOE";
542 st,bank-name = "GPIOF";
554 st,bank-name = "GPIOG";
566 st,bank-name = "GPIOH";
[all …]
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| A D | stm32mp15xx-osd32.dtsi | 18 compatible = "st,stpmic1";
54 st,mask-reset;
162 st,non-secure-otp;
167 st,digbypass;
184 st,clksrc = <
196 st,clkdiv = <
210 st,pkcs = <
249 pll1: st,pll@0 {
257 pll2: st,pll@1 {
265 pll3: st,pll@2 {
[all …]
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| A D | stm32mp157c-odyssey-som.dtsi | 33 st,non-secure-otp;
38 st,digbypass;
113 st,mask-reset;
206 st,clksrc = <
218 st,clkdiv = <
232 st,pkcs = <
271 pll1: st,pll@0 {
279 pll2: st,pll@1 {
287 pll3: st,pll@2 {
295 pll4: st,pll@3 {
[all …]
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| A D | stm32mp15xx-dhcom-som.dtsi | 22 st,non-secure-otp;
86 st,mask-reset;
189 st,clksrc = <
201 st,clkdiv = <
215 st,pkcs = <
254 pll1: st,pll@0 {
262 pll2: st,pll@1 {
270 pll3: st,pll@2 {
297 st,sig-dir;
298 st,neg-edge;
[all …]
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| A D | stm32mp15xx-dkx.dtsi | 28 st,non-secure-otp;
33 st,digbypass;
104 st,mask-reset;
191 st,clksrc = <
203 st,clkdiv = <
217 st,pkcs = <
256 pll1: st,pll@0 {
264 pll2: st,pll@1 {
272 pll3: st,pll@2 {
280 pll4: st,pll@3 {
[all …]
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| A D | stm32mp13-ddr.dtsi | 7 st,mem-name = DDR_MEM_NAME;
8 st,mem-speed = <DDR_MEM_SPEED>;
9 st,mem-size = <DDR_MEM_SIZE>;
11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
80 st,phy-reg = <
92 st,phy-timing = <
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| A D | stm32mp15xx-dhcor-som.dtsi | 41 compatible = "st,stpmic1";
110 st,regulator-sink-source;
184 st,clksrc = <
196 st,clkdiv = <
210 st,pkcs = <
249 pll1: st,pll@0 {
250 compatible = "st,stm32mp1-pll";
257 pll2: st,pll@1 {
258 compatible = "st,stm32mp1-pll";
265 pll3: st,pll@2 {
[all …]
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| A D | stm32mp13xf.dtsi | 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
11 compatible = "st,stm32-saes";
19 compatible = "st,stm32-pka64";
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| A D | stm32mp157a-dk1.dts | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
16 compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
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| A D | stm32mp13xc.dtsi | 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
12 compatible = "st,stm32-saes";
20 compatible = "st,stm32-pka64";
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| A D | stm32mp157c-dk2.dts | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
17 compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
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| A D | stm32mp157c-ev1.dts | 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
12 compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
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| A D | stm32mp15xc.dtsi | 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
10 compatible = "st,stm32mp1-cryp";
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| /arm-trusted-firmware-2.8.0/plat/st/stm32mp1/sp_min/ |
| A D | sp_min-stm32mp1.mk | 19 BL32_SOURCES += drivers/st/etzpc/etzpc.c \
21 plat/st/stm32mp1/sp_min/sp_min_setup.c \
22 plat/st/stm32mp1/stm32mp1_pm.c \
23 plat/st/stm32mp1/stm32mp1_shared_resources.c \
24 plat/st/stm32mp1/stm32mp1_topology.c
35 plat/st/stm32mp1/stm32mp1_gic.c
48 BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
49 plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
50 plat/st/stm32mp1/stm32mp1_scmi.c
|
| /arm-trusted-firmware-2.8.0/drivers/rpi3/mailbox/ |
| A D | rpi3_mbox.c | 24 uint32_t st, data; in rpi3_vc_mailbox_request_send() local
38 st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX1_STATUS_OFFSET); in rpi3_vc_mailbox_request_send()
46 } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) == 0U); in rpi3_vc_mailbox_request_send()
56 st = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_STATUS_OFFSET); in rpi3_vc_mailbox_request_send()
64 } while ((st & RPI3_MBOX_STATUS_EMPTY_MASK) != 0U); in rpi3_vc_mailbox_request_send()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/px30/drivers/secure/ |
| A D | secure.c | 22 uintptr_t st, size_t sz) in secure_ddr_region() argument
24 uintptr_t ed = st + sz; in secure_ddr_region()
29 assert(st < ed); in secure_ddr_region()
32 assert(st % SIZE_M(1) == 0); in secure_ddr_region()
35 st_mb = st / SIZE_M(1); in secure_ddr_region()
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| /arm-trusted-firmware-2.8.0/plat/mediatek/drivers/cirq/ |
| A D | mt_cirq.c | 301 uint32_t addr, st, val; in mt_irq_get_en() local
304 st = mmio_read_32(addr); in mt_irq_get_en()
306 val = (st >> (irq % 32U)) & 1U; in mt_irq_get_en()
450 uint32_t st; in mt_cirq_enable() local
455 st = mmio_read_32(CIRQ_CON); in mt_cirq_enable()
459 st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS); in mt_cirq_enable()
469 uint32_t st; in mt_cirq_disable() local
471 st = mmio_read_32(CIRQ_CON); in mt_cirq_disable()
544 uint32_t st; in mt_cirq_sw_reset() local
546 st = mmio_read_32(CIRQ_CON); in mt_cirq_sw_reset()
[all …]
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3288/drivers/secure/ |
| A D | secure.c | 50 static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz) in sgrf_ddr_rgn_config() argument
52 uintptr_t ed = st + sz; in sgrf_ddr_rgn_config()
56 assert(st < ed); in sgrf_ddr_rgn_config()
59 assert(st % SIZE_M(1) == 0); in sgrf_ddr_rgn_config()
62 st_mb = st / SIZE_M(1); in sgrf_ddr_rgn_config()
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| /arm-trusted-firmware-2.8.0/include/lib/libc/ |
| A D | stddef.h | 25 #define offsetof(st, m) __builtin_offsetof(st, m) argument
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/secure/ |
| A D | secure.c | 58 uintptr_t st, size_t sz) in sgrf_ddr_rgn_config() argument
60 uintptr_t ed = st + sz; in sgrf_ddr_rgn_config()
64 assert(st < ed); in sgrf_ddr_rgn_config()
67 assert(st % SIZE_M(1) == 0); in sgrf_ddr_rgn_config()
70 st_mb = st / SIZE_M(1); in sgrf_ddr_rgn_config()
|