/arm-trusted-firmware-2.8.0/lib/psci/ |
A D | psci_stat.c | 175 static int psci_get_stat(u_register_t target_cpu, unsigned int power_state, in psci_get_stat() argument 185 target_idx = (unsigned int) plat_core_pos_by_mpidr(target_cpu); in psci_get_stat() 194 target_cpu, power_state, &state_info); in psci_get_stat() 227 u_register_t psci_stat_residency(u_register_t target_cpu, in psci_stat_residency() argument 231 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); in psci_stat_residency() 240 u_register_t psci_stat_count(u_register_t target_cpu, in psci_stat_count() argument 244 int rc = psci_get_stat(target_cpu, power_state, &psci_stat); in psci_stat_count()
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A D | psci_on.c | 59 int psci_cpu_on_start(u_register_t target_cpu, in psci_cpu_on_start() argument 64 int ret = plat_core_pos_by_mpidr(target_cpu); in psci_cpu_on_start() 110 psci_spd_pm->svc_on(target_cpu); in psci_cpu_on_start() 146 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); in psci_cpu_on_start()
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A D | psci_main.c | 24 int psci_cpu_on(u_register_t target_cpu, in psci_cpu_on() argument 33 rc = psci_validate_mpidr(target_cpu); in psci_cpu_on() 46 return psci_cpu_on_start(target_cpu, &ep); in psci_cpu_on() 257 int psci_migrate(u_register_t target_cpu) in psci_migrate() argument 275 rc = psci_validate_mpidr(target_cpu); in psci_migrate() 281 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); in psci_migrate() 310 int psci_node_hw_state(u_register_t target_cpu, in psci_node_hw_state() argument 316 rc = psci_validate_mpidr(target_cpu); in psci_node_hw_state() 329 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); in psci_node_hw_state()
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A D | psci_private.h | 308 int psci_cpu_on_start(u_register_t target_cpu, 338 u_register_t psci_stat_residency(u_register_t target_cpu, 340 u_register_t psci_stat_count(u_register_t target_cpu,
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/arm-trusted-firmware-2.8.0/plat/xilinx/common/ |
A D | plat_startup.c | 179 int32_t target_estate, target_secure, target_cpu; in fsbl_atf_handover() local 186 target_cpu = get_fsbl_cpu(&ATFHandoffParams->partition[i]); in fsbl_atf_handover() 187 if (target_cpu != FSBL_FLAGS_A53_0) { in fsbl_atf_handover() 188 WARN("BL31: invalid target CPU (%i)\n", target_cpu); in fsbl_atf_handover()
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/arm-trusted-firmware-2.8.0/include/lib/psci/ |
A D | psci.h | 334 int psci_cpu_on(u_register_t target_cpu, 344 int psci_migrate(u_register_t target_cpu); 347 int psci_node_hw_state(u_register_t target_cpu,
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A D | psci_lib.h | 24 void (*svc_on)(u_register_t target_cpu);
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/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/ |
A D | fvp_pm.c | 348 static int fvp_node_hw_state(u_register_t target_cpu, in fvp_node_hw_state() argument 366 psysr = fvp_pwrc_read_psysr(target_cpu); in fvp_node_hw_state()
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/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/ |
A D | plat_psci_handlers.c | 323 uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; in tegra_soc_pwr_domain_on() local 334 target_cpu += (target_cluster << 1U); in tegra_soc_pwr_domain_on() 336 ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); in tegra_soc_pwr_domain_on()
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/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/ |
A D | plat_psci_handlers.c | 351 uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; in tegra_soc_pwr_domain_on() local 362 target_cpu |= (target_cluster << 2); in tegra_soc_pwr_domain_on() 364 (void)mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); in tegra_soc_pwr_domain_on()
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/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/ |
A D | stm32mp1_pm.c | 194 static int stm32_node_hw_state(u_register_t target_cpu, in stm32_node_hw_state() argument
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/arm-trusted-firmware-2.8.0/services/spd/opteed/ |
A D | opteed_pm.c | 21 static void opteed_cpu_on_handler(u_register_t target_cpu) in opteed_cpu_on_handler() argument
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/arm-trusted-firmware-2.8.0/services/spd/tspd/ |
A D | tspd_pm.c | 22 static void tspd_cpu_on_handler(u_register_t target_cpu) in tspd_cpu_on_handler() argument
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/arm-trusted-firmware-2.8.0/docs/getting_started/ |
A D | psci-lib-integration-guide.rst | 460 void (*svc_on)(u_register_t target_cpu);
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