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Searched refs:target_masks_num (Results 1 – 12 of 12) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/
A Dpoplar_gicv2.c29 .target_masks_num = ARRAY_SIZE(target_mask_array),
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/
A Dtegra_gicv2.c40 tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks); in tegra_gic_setup()
/arm-trusted-firmware-2.8.0/drivers/nxp/gic/
A Dls_gicv2.c27 ls_gic_data.target_masks_num = plat_core_count; in plat_ls_gic_driver_init()
/arm-trusted-firmware-2.8.0/plat/arm/common/
A Darm_gicv2.c40 .target_masks_num = ARRAY_SIZE(target_mask_array),
/arm-trusted-firmware-2.8.0/drivers/arm/gic/v2/
A Dgicv2_main.c301 assert(proc_num < driver_data->target_masks_num); in gicv2_set_pe_target_mask()
435 assert(proc_num < (int)driver_data->target_masks_num); in gicv2_raise_sgi()
472 assert(driver_data->target_masks_num < INT_MAX); in gicv2_set_spi_routing()
473 assert(proc_num < (int)driver_data->target_masks_num); in gicv2_set_spi_routing()
/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_gic.c39 .target_masks_num = ARRAY_SIZE(target_mask_array),
/arm-trusted-firmware-2.8.0/plat/marvell/armada/common/
A Dmarvell_gicv2.c63 .target_masks_num = ARRAY_SIZE(target_mask_array),
/arm-trusted-firmware-2.8.0/plat/qemu/common/sp_min/
A Dsp_min_setup.c67 .target_masks_num = ARRAY_SIZE(target_mask_array),
/arm-trusted-firmware-2.8.0/plat/intel/soc/agilex/
A Dbl31_plat_setup.c97 .target_masks_num = ARRAY_SIZE(target_mask_array),
/arm-trusted-firmware-2.8.0/include/drivers/arm/
A Dgicv2.h166 unsigned int target_masks_num; member
/arm-trusted-firmware-2.8.0/plat/intel/soc/n5x/
A Dbl31_plat_setup.c98 .target_masks_num = ARRAY_SIZE(target_mask_array),
/arm-trusted-firmware-2.8.0/plat/intel/soc/stratix10/
A Dbl31_plat_setup.c105 .target_masks_num = ARRAY_SIZE(target_mask_array),

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