Searched refs:timing (Results 1 – 17 of 17) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/ |
| A D | dram.c | 48 void dram_umctl2_init(struct dram_timing_info *timing) in dram_umctl2_init() argument
50 struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; in dram_umctl2_init()
53 for (i = 0U; i < timing->ddrc_cfg_num; i++) { in dram_umctl2_init()
63 void dram_phy_init(struct dram_timing_info *timing) in dram_phy_init() argument
65 struct dram_cfg_param *cfg = timing->ddrphy_cfg; in dram_phy_init()
69 cfg = timing->ddrphy_cfg; in dram_phy_init()
70 for (i = 0U; i < timing->ddrphy_cfg_num; i++) { in dram_phy_init()
76 cfg = timing->ddrphy_trained_csr; in dram_phy_init()
77 for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) { in dram_phy_init()
83 cfg = timing->ddrphy_pie; in dram_phy_init()
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/ |
| A D | dram.h | 65 void dram_umctl2_init(struct dram_timing_info *timing);
66 void dram_phy_init(struct dram_timing_info *timing);
|
| /arm-trusted-firmware-2.8.0/drivers/st/fmc/ |
| A D | stm32_fmc2_nand.c | 172 timing = div_round_up(tar, hclkp) - 1U; in stm32_fmc2_nand_setup_timing()
176 timing = div_round_up(tclr, hclkp) - 1U; in stm32_fmc2_nand_setup_timing()
190 timing = div_round_up(twait, hclkp); in stm32_fmc2_nand_setup_timing()
191 tims.twait = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing()
207 timing = div_round_up(tset_mem, hclkp); in stm32_fmc2_nand_setup_timing()
208 tims.tset_mem = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing()
229 timing = div_round_up(thold_mem, hclkp); in stm32_fmc2_nand_setup_timing()
230 tims.thold_mem = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing()
252 timing = div_round_up(tset_att, hclkp); in stm32_fmc2_nand_setup_timing()
253 tims.tset_att = CLAMP(timing, 1UL, in stm32_fmc2_nand_setup_timing()
[all …]
|
| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | stm32mp15-ddr.dtsi | 39 st,ctl-timing = <
100 st,phy-timing = <
|
| A D | stm32mp13-ddr.dtsi | 39 st,ctl-timing = <
92 st,phy-timing = <
|
| A D | stm32mp13-ddr3-1x4Gb-1066-binF.dtsi | 14 * timing mode optimized
|
| A D | stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 14 * timing mode optimized
|
| A D | tc.dts | 358 panel-timing {
|
| /arm-trusted-firmware-2.8.0/drivers/st/ddr/ |
| A D | stm32mp1_ram.c | 64 CTL_PARAM(timing), in stm32mp1_ddr_setup()
68 PHY_PARAM(timing), in stm32mp1_ddr_setup()
|
| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-5.rst | 6 | | secure world timing information |
18 | Impact | Leakage of sensitive secure world timing information |
37 cause leakage of secure world timing information. This register should be added
|
| A D | security-advisory-tfv-6.rst | 6 | | vulnerabilities using cache timing side-channels |
|
| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | security-hardening.rst | 28 Preventing Secure-world timing information leakage via PMU counters
32 world from making it leak timing information. In general, higher privilege
44 Secure and Non-secure state. Thus, it attempts to leak timing information from
72 would allow it to carry out side-channel timing attacks against the Secure
|
| A D | security.rst | 61 | | world timing information |
64 | | vulnerabilities using cache timing side-channels |
|
| /arm-trusted-firmware-2.8.0/drivers/st/i2c/ |
| A D | stm32_i2c.c | 150 uint32_t timing = I2C_TIMING; in stm32_i2c_init() local
169 timing & TIMINGR_CLEAR_MASK); in stm32_i2c_init()
|
| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | threat_model.rst | 511 | | | Do not log high precision timing information. |
843 | | side-channel timing attacks against TF-A. |
|
| A D | threat_model_spm.rst | 558 | | Spectre, Meltdown or other cache timing |
|
| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | xlat-tables-lib-v2-design.rst | 115 timing, the MPU hardware does not involve memory-resident translation tables.
|
Completed in 18 milliseconds