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Searched refs:timing_cfg (Results 1 – 11 of 11) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046ardb/
A Dddr_init.c26 .timing_cfg[0] = U(0xD1770018),
27 .timing_cfg[1] = U(0xF2FC9245),
28 .timing_cfg[2] = U(0x594197),
29 .timing_cfg[3] = U(0x2101100),
30 .timing_cfg[4] = U(0x220002),
31 .timing_cfg[5] = U(0x5401400),
32 .timing_cfg[7] = U(0x26600000),
33 .timing_cfg[8] = U(0x5446A00),
73 .timing_cfg[2] = U(0x512153),
123 .timing_cfg[6] = U(0x0),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160aqds/
A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2162aqds/
A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ls1046afrwy/
A Dddr_init.c25 .timing_cfg[0] = U(0xFA550018),
26 .timing_cfg[1] = U(0xBAB40C52),
27 .timing_cfg[2] = U(0x0048C11C),
28 .timing_cfg[3] = U(0x01111000),
29 .timing_cfg[4] = U(0x00000002),
30 .timing_cfg[5] = U(0x03401400),
31 .timing_cfg[6] = U(0x0),
32 .timing_cfg[7] = U(0x23300000),
33 .timing_cfg[8] = U(0x02116600),
34 .timing_cfg[9] = U(0x0),
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ls1043ardb/
A Dddr_init.c22 .timing_cfg[0] = U(0x91550018),
23 .timing_cfg[1] = U(0xBBB48C42),
24 .timing_cfg[2] = U(0x48C111),
25 .timing_cfg[3] = U(0x10C1000),
26 .timing_cfg[4] = U(0x2),
27 .timing_cfg[5] = U(0x3401400),
28 .timing_cfg[7] = U(0x13300000),
29 .timing_cfg[8] = U(0x2115600),
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ls1028ardb/
A Dddr_init.c20 .timing_cfg[0] = U(0x91550018),
21 .timing_cfg[1] = U(0xBAB40C42),
22 .timing_cfg[2] = U(0x48C111),
23 .timing_cfg[3] = U(0x1111000),
24 .timing_cfg[4] = U(0x2),
25 .timing_cfg[5] = U(0x3401400),
26 .timing_cfg[7] = U(0x23300000),
27 .timing_cfg[8] = U(0x2114600),
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/lx2160ardb/
A Dddr_init.c32 .timing_cfg[0] = U(0xFF550018),
33 .timing_cfg[1] = U(0xBAB48C42),
34 .timing_cfg[2] = U(0x48C111),
35 .timing_cfg[3] = U(0x10C1000),
36 .timing_cfg[4] = U(0x2),
37 .timing_cfg[5] = U(0x3401400),
38 .timing_cfg[7] = U(0x13300000),
39 .timing_cfg[8] = U(0x2114600),
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/
A Dregs.c228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) | in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) | in cal_timing_cfg()
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) | in cal_timing_cfg()
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) | in cal_timing_cfg()
[all …]
A Dddrc.c228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]); in ddrc_set_regs()
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]); in ddrc_set_regs()
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]); in ddrc_set_regs()
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]); in ddrc_set_regs()
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]); in ddrc_set_regs()
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]); in ddrc_set_regs()
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]); in ddrc_set_regs()
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]); in ddrc_set_regs()
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]); in ddrc_set_regs()
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]); in ddrc_set_regs()
/arm-trusted-firmware-2.8.0/include/drivers/nxp/ddr/
A Dddr.h56 unsigned int timing_cfg[10]; member
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/phy-gen2/
A Dphy.c2615 tcfg0 = regs->timing_cfg[0]; in compute_ddr_phy()
2616 tcfg4 = regs->timing_cfg[4]; in compute_ddr_phy()
2620 regs->timing_cfg[0] = tcfg0; in compute_ddr_phy()
2621 regs->timing_cfg[4] = tcfg4; in compute_ddr_phy()

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