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/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/
A Ddram_spec_timing.c216 tmp = 0; in ddr3_get_parameter()
218 tmp = 1; in ddr3_get_parameter()
220 tmp = 2; in ddr3_get_parameter()
222 tmp = 3; in ddr3_get_parameter()
224 tmp = 4; in ddr3_get_parameter()
226 tmp = 5; in ddr3_get_parameter()
228 tmp = 6; in ddr3_get_parameter()
283 tmp = tmp - 4; in ddr3_get_parameter()
285 tmp += (tmp & 0x1) ? 1 : 0; in ddr3_get_parameter()
286 tmp = tmp >> 1; in ddr3_get_parameter()
[all …]
A Ddfs.c668 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; in gen_rk3399_ctl_params_f0()
682 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; in gen_rk3399_ctl_params_f0()
710 tmp = tmp + 18; in gen_rk3399_ctl_params_f0()
917 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; in gen_rk3399_ctl_params_f1()
932 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; in gen_rk3399_ctl_params_f1()
960 tmp = tmp + 18; in gen_rk3399_ctl_params_f1()
1141 tmp = tmp + 1; in gen_rk3399_pi_params_f0()
1143 tmp = tmp + 8; in gen_rk3399_pi_params_f0()
1302 tmp = tmp + 18; in gen_rk3399_pi_params_f1()
1320 tmp = tmp + 1; in gen_rk3399_pi_params_f1()
[all …]
A Dsuspend.c191 uint32_t i, tmp; in data_training() local
246 if ((((tmp >> 11) & 0x1) == 0x1) && in data_training()
248 (((tmp >> 5) & 0x1) == 0x0) && in data_training()
292 (((tmp >> 4) & 0x1) == 0x0) && in data_training()
340 if ((((tmp >> 9) & 0x1) == 0x1) && in data_training()
342 (((tmp >> 3) & 0x1) == 0x0) && in data_training()
375 if ((((tmp >> 8) & 0x1) == 0x1) && in data_training()
377 (((tmp >> 2) & 0x1) == 0x0)) in data_training()
412 (((tmp >> 6) & 0x1) == 0x0)) in data_training()
495 uint32_t tmp, tmp1, tmp2, i; in pctl_cfg() local
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/arm-trusted-firmware-2.8.0/plat/rockchip/px30/drivers/soc/
A Dsoc.c88 uint32_t tmp; in soc_reset_config_all() local
91 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in soc_reset_config_all()
92 tmp |= CRU_GLB_RST_TSADC_FST | CRU_GLB_RST_WDT_FST; in soc_reset_config_all()
93 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in soc_reset_config_all()
106 uint32_t tmp; in px30_soc_reset_config() local
109 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in px30_soc_reset_config()
111 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in px30_soc_reset_config()
113 tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH); in px30_soc_reset_config()
114 tmp &= ~CRU_GLB_CNT_RST_MSK; in px30_soc_reset_config()
115 tmp |= (CRU_GLB_CNT_RST_1MS / 2); in px30_soc_reset_config()
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/juno/
A Djuno_trusted_boot.c29 uint32_t *src, tmp; in juno_get_rotpk_info_regs() local
70 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
72 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in juno_get_rotpk_info_regs()
73 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in juno_get_rotpk_info_regs()
74 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in juno_get_rotpk_info_regs()
75 *dst++ = (uint8_t)(tmp & 0xFF); in juno_get_rotpk_info_regs()
81 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
82 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in juno_get_rotpk_info_regs()
83 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in juno_get_rotpk_info_regs()
84 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in juno_get_rotpk_info_regs()
[all …]
/arm-trusted-firmware-2.8.0/lib/zlib/
A Dadler32.c29 unsigned long tmp = a >> 16; \
31 a += (tmp << 4) - tmp; \
45 z_off64_t tmp = a >> 32; \
47 a += (tmp << 8) - (tmp << 5) + tmp; \
48 tmp = a >> 16; \
50 a += (tmp << 4) - tmp; \
51 tmp = a >> 16; \
53 a += (tmp << 4) - tmp; \
/arm-trusted-firmware-2.8.0/include/arch/aarch64/
A Dasm_macros.S38 .macro dcache_line_size reg, tmp
39 mrs \tmp, ctr_el0
40 ubfx \tmp, \tmp, #16, #4
42 lsl \reg, \reg, \tmp
46 .macro icache_line_size reg, tmp
47 mrs \tmp, ctr_el0
48 and \tmp, \tmp, #0xf
50 lsl \reg, \reg, \tmp
/arm-trusted-firmware-2.8.0/include/arch/aarch32/
A Dasm_macros.S49 .macro dcache_line_size reg, tmp
50 ldcopr \tmp, CTR
51 ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH
53 lsl \reg, \reg, \tmp
56 .macro icache_line_size reg, tmp
57 ldcopr \tmp, CTR
58 and \tmp, \tmp, #CTR_IMINLINE_MASK
60 lsl \reg, \reg, \tmp
/arm-trusted-firmware-2.8.0/include/lib/libfdt/
A Dlibfdt.h1320 fdt32_t tmp = cpu_to_fdt32(val); in fdt_setprop_inplace_u32() local
1321 return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_setprop_inplace_u32()
1355 fdt64_t tmp = cpu_to_fdt64(val); in fdt_setprop_inplace_u64() local
1356 return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_setprop_inplace_u64()
1475 fdt32_t tmp = cpu_to_fdt32(val); in fdt_property_u32() local
1476 return fdt_property(fdt, name, &tmp, sizeof(tmp)); in fdt_property_u32()
1481 return fdt_property(fdt, name, &tmp, sizeof(tmp)); in fdt_property_u64()
1688 return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_setprop_u32()
1723 return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_setprop_u64()
1866 return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_appendprop_u32()
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/imx8qx/
A Dimx8qx_bl31_setup.c106 unsigned int diff1, diff2, tmp, rate; in lpuart32_serial_setbrg() local
138 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); in lpuart32_serial_setbrg()
141 tmp |= LPUART_BAUD_BOTHEDGE_MASK; in lpuart32_serial_setbrg()
143 tmp &= ~LPUART_BAUD_OSR_MASK; in lpuart32_serial_setbrg()
144 tmp |= LPUART_BAUD_OSR(osr - 1); in lpuart32_serial_setbrg()
145 tmp &= ~LPUART_BAUD_SBR_MASK; in lpuart32_serial_setbrg()
146 tmp |= LPUART_BAUD_SBR(sbr); in lpuart32_serial_setbrg()
151 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); in lpuart32_serial_setbrg()
156 unsigned int tmp; in lpuart32_serial_init() local
159 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); in lpuart32_serial_init()
[all …]
/arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/driver/ext_sram_init/
A Dext_sram_init.c181 unsigned int val, tmp; in brcm_stingray_pnor_sram_init() local
215 tmp = 0x0; in brcm_stingray_pnor_sram_init()
217 tmp |= (val & PNOR_REG_PERIPH_IDx_MASK); in brcm_stingray_pnor_sram_init()
219 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 8); in brcm_stingray_pnor_sram_init()
221 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 16); in brcm_stingray_pnor_sram_init()
223 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 24); in brcm_stingray_pnor_sram_init()
224 INFO(" -- pnor primecell_id = 0x%x\n", tmp); in brcm_stingray_pnor_sram_init()
270 tmp = 0; in brcm_stingray_pnor_sram_init()
278 tmp++; in brcm_stingray_pnor_sram_init()
281 tmp, (NOR_SIZE / SRAM_CHECKS_GRANUL)); in brcm_stingray_pnor_sram_init()
[all …]
/arm-trusted-firmware-2.8.0/drivers/renesas/common/ddr/ddr_b/
A Dboot_init_dram.c1660 tmp = tmp >> 4; in ddr_config_sub()
1702 tmp = tmp >> 4; in ddr_config_sub()
1715 tmp = tmp >> 4; in ddr_config_sub()
2127 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); in dbsc_regset()
2136 tmp[2] = tmp[3]; in dbsc_regset()
2138 tmp[2] = tmp[3] + 2; in dbsc_regset()
2147 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); in dbsc_regset()
2228 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); in dbsc_regset()
2244 (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); in dbsc_regset()
4034 tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); in rx_offset_cal_hw()
[all …]
/arm-trusted-firmware-2.8.0/plat/st/common/
A Dstm32mp_trusted_boot.c49 uint32_t tmp; in copy_hash_from_otp() local
58 tmp = bswap32(otp_val); in copy_hash_from_otp()
59 memcpy(hash + i * sizeof(uint32_t), &tmp, sizeof(tmp)); in copy_hash_from_otp()
62 first = tmp; in copy_hash_from_otp()
70 if ((tmp != 0U) && (tmp != 0xFFFFFFFFU) && (tmp != first)) { in copy_hash_from_otp()
/arm-trusted-firmware-2.8.0/lib/aarch32/
A Dmisc_helpers.S59 tmp .req r12 /* Temporary scratch register */
79 orr tmp, cursor, #(8-1)
80 adds tmp, tmp, #1
84 cmp tmp, stop_address
90 cmp cursor, tmp
97 bic tmp, stop_address, #(8-1)
99 cmp cursor, tmp
105 cmp cursor, tmp
128 .unreq tmp
/arm-trusted-firmware-2.8.0/plat/imx/imx8qm/
A Dimx8qm_bl31_setup.c95 unsigned int diff1, diff2, tmp, rate; in lpuart32_serial_setbrg() local
127 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); in lpuart32_serial_setbrg()
130 tmp |= LPUART_BAUD_BOTHEDGE_MASK; in lpuart32_serial_setbrg()
132 tmp &= ~LPUART_BAUD_OSR_MASK; in lpuart32_serial_setbrg()
133 tmp |= LPUART_BAUD_OSR(osr - 1); in lpuart32_serial_setbrg()
134 tmp &= ~LPUART_BAUD_SBR_MASK; in lpuart32_serial_setbrg()
135 tmp |= LPUART_BAUD_SBR(sbr); in lpuart32_serial_setbrg()
140 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); in lpuart32_serial_setbrg()
145 unsigned int tmp; in lpuart32_serial_init() local
148 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); in lpuart32_serial_init()
[all …]
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/
A Dddrc.c201 unsigned int tmp; in ddrc_set_regs() local
363 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
364 tmp &= U(0xff0fff00); in ddrc_set_regs()
369 tmp &= ~0xff; in ddrc_set_regs()
370 tmp |= regs->debug[28] & 0xff; in ddrc_set_regs()
374 ddr_out32(&ddr->debug[28], tmp); in ddrc_set_regs()
551 check = (tmp == DDR_DBUS_64) ? 4 : ((tmp == DDR_DBUS_32) ? 2 : 1); in ddrc_set_regs()
556 min((tmp >> 24) & 0xff, (tmp >> 8) & 0xff)); in ddrc_set_regs()
558 max((tmp >> 24) & 0xff, (tmp >> 8) & 0xff)); in ddrc_set_regs()
567 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/common/
A Darm_nor_psci_mem_protect.c40 int tmp; in arm_psci_read_mem_protect() local
42 tmp = *(int *) PLAT_ARM_MEM_PROT_ADDR; in arm_psci_read_mem_protect()
43 *enabled = (tmp == 1) ? 1 : 0; in arm_psci_read_mem_protect()
/arm-trusted-firmware-2.8.0/plat/qemu/common/
A Dqemu_spm.c65 spm_mm_mp_info_t *tmp = mp_info; in qemu_initialize_mp_info() local
69 tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j; in qemu_initialize_mp_info()
74 tmp->linear_id = 0; in qemu_initialize_mp_info()
75 tmp->flags = 0; in qemu_initialize_mp_info()
76 tmp++; in qemu_initialize_mp_info()
/arm-trusted-firmware-2.8.0/plat/socionext/uniphier/
A Duniphier_scp.c33 uint32_t tmp; in uniphier_scp_start() local
39 tmp = mmio_read_32(UNIPHIER_ROM_RSV3); in uniphier_scp_start()
40 } while (!(tmp & BIT(8))); in uniphier_scp_start()
42 mmio_write_32(UNIPHIER_ROM_RSV3, tmp | BIT(9)); in uniphier_scp_start()
A Duniphier_emmc.c195 uint8_t tmp; in uniphier_emmc_load_image() local
203 tmp = mmio_read_8(host_base + SDHCI_HOST_CONTROL); in uniphier_emmc_load_image()
204 tmp &= ~SDHCI_CTRL_DMA_MASK; in uniphier_emmc_load_image()
205 tmp |= SDHCI_CTRL_SDMA; in uniphier_emmc_load_image()
206 mmio_write_8(host_base + SDHCI_HOST_CONTROL, tmp); in uniphier_emmc_load_image()
208 tmp = mmio_read_8(host_base + SDHCI_BLOCK_GAP_CONTROL); in uniphier_emmc_load_image()
209 tmp &= ~1; /* clear Stop At Block Gap Request */ in uniphier_emmc_load_image()
210 mmio_write_8(host_base + SDHCI_BLOCK_GAP_CONTROL, tmp); in uniphier_emmc_load_image()
/arm-trusted-firmware-2.8.0/plat/brcm/board/common/
A Dboard_arm_trusted_boot.c145 uint32_t *src, tmp; in plat_get_rotpk_info() local
177 tmp = src[words - 1 - i]; in plat_get_rotpk_info()
179 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in plat_get_rotpk_info()
180 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in plat_get_rotpk_info()
181 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in plat_get_rotpk_info()
182 *dst++ = (uint8_t)(tmp & 0xFF); in plat_get_rotpk_info()
188 tmp = src[words - 1 - i]; in plat_get_rotpk_info()
189 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in plat_get_rotpk_info()
190 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in plat_get_rotpk_info()
191 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in plat_get_rotpk_info()
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/common/
A Dboard_arm_trusted_boot.c64 uint32_t *src, tmp; in arm_get_rotpk_info_regs() local
80 tmp = src[words - 1 - i]; in arm_get_rotpk_info_regs()
82 *dst++ = (uint8_t)(tmp & 0xFF); in arm_get_rotpk_info_regs()
83 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in arm_get_rotpk_info_regs()
84 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in arm_get_rotpk_info_regs()
85 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in arm_get_rotpk_info_regs()
/arm-trusted-firmware-2.8.0/drivers/nxp/crypto/caam/src/
A Dcaam.c71 uint32_t tmp = sec_in32((g_nxp_caam_addr + SEC_REG_JRSTARTR_OFFSET)); in start_jr() local
89 tmp |= JRSTARTR_STARTJR0; in start_jr()
92 tmp |= JRSTARTR_STARTJR1; in start_jr()
95 tmp |= JRSTARTR_STARTJR2; in start_jr()
98 tmp |= JRSTARTR_STARTJR3; in start_jr()
104 sec_out32((g_nxp_caam_addr + SEC_REG_JRSTARTR_OFFSET), tmp); in start_jr()
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/fsl-mmdc/
A Dfsl_mmdc.c43 unsigned int tmp; in mmdc_init() local
65 tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1); in mmdc_init()
66 ddr_out32(&mmdc->mdctl, tmp); in mmdc_init()
74 ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0); in mmdc_init()
76 ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1); in mmdc_init()
/arm-trusted-firmware-2.8.0/lib/romlib/
A Dgen_combined_bl1_romlib.sh52 cat $bin_path/romlib/romlib.bin) > $bin_path/$$.tmp &&
53 mv $bin_path/$$.tmp $bin_path/$output

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