| /arm-trusted-firmware-2.8.0/include/arch/aarch32/ |
| A D | asm_macros.S | 219 .macro softudiv div:req,top:req,bot:req,temp:req
222 cmp \temp, \top, lsr #1
225 cmp \temp, \top, lsr #1
230 cmp \top, \temp
231 subcs \top, \top,\temp
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| /arm-trusted-firmware-2.8.0/plat/rockchip/px30/drivers/secure/ |
| A D | secure.h | 35 #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) argument
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| /arm-trusted-firmware-2.8.0/plat/rockchip/common/drivers/parameter/ |
| A D | ddr_parameter.c | 53 uint64_t base, top; in ddr_region_usage_parse() local
77 top = base + mmio_read_64(addr + size_offset); in ddr_region_usage_parse()
83 p.ns_top[i] = RG_SIZE_MB(top); in ddr_region_usage_parse()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/soc/ |
| A D | soc.h | 102 #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) argument
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| /arm-trusted-firmware-2.8.0/drivers/renesas/common/emmc/ |
| A D | emmc_utility.c | 79 uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom) in emmc_bit_field() argument
83 uint32_t index_top = (uint32_t) (15 - (top >> 3)); in emmc_bit_field()
104 value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1)); in emmc_bit_field()
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| A D | emmc_def.h | 51 uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom);
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | n1sdp-single-chip.dts | 23 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
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| A D | stm32mp15-fw-config.dtsi | 17 /* OP-TEE reserved shared memory: located at DDR top or null size */
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| /arm-trusted-firmware-2.8.0/docs/perf/ |
| A D | performance-monitoring-unit.rst | 120 - The effects of ``PMEVTYPER<n>`` are applied on top of this.
145 - The effects of ``PMCNTENSET`` and ``PMCR.DP`` are applied on top of this.
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | warp7.rst | 50 The following commands assume that a directory exits in the top-level TFA build
159 arm-trusted-firmware top-level directory.
187 # Copy signed BL2 to top-level directory
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| A D | qemu-sbsa.rst | 42 Need to copy them into top directory for EDK2 compilation.
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| A D | xilinx-zynqmp.rst | 73 common to the cluster are grouped in the power domain on the top.
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| A D | poplar.rst | 9 of running any commercial set-top solution based on Linux or Android.
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | exception-handling.rst | 143 top-level handler for interrupts that target EL3, as described in the
187 to use the top *n* of the 7 remaining bits to identify and assign interrupts
199 that at least ``n+1`` top bits of GIC priority are writeable.
279 The parameters are as obtained from the top-level :ref:`EL3 interrupt handler
535 #. The |EHF|, during its initialisation, registers a top-level interrupt handler
542 #. The top-level EL3 interrupt handler executes. The handler acknowledges the
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| A D | ras.rst | 114 ``cookie``, and ``handle`` parameters from the :ref:`top-level exception handler
208 top-level RAS exception handler. ``ras_ea_handler`` is responsible for iterating
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| A D | romlib-design.rst | 121 On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM.
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| A D | sdei.rst | 337 To work this around, it's advised that the top-level event handlers are
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| A D | xlat-tables-lib-v2-design.rst | 395 directly maps regions by "base" and "limit" (bottom and top) addresses.
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | docs-build.rst | 73 top-level Makefile for |TF-A| itself.
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| A D | psci-lib-integration-guide.rst | 252 This function is the top level handler for SMCs which fall within the
278 mentioned at top of this section. This function must be called with Data cache
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| /arm-trusted-firmware-2.8.0/ |
| A D | changelog.yaml | 8 # The following block describes the top-level sections of the changelog. Commits are categorized
9 # into these top-level sections based on the commit message "type":
71 # any of the top-level sections, and describe the individual components that a change may relate to.
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | measured_boot_poc.rst | 18 a firmware TPM (fTPM) service implemented on top of OP-TEE.
32 The PoC is built on top of the `OP-TEE Toolkit`_, which has support to build
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| /arm-trusted-firmware-2.8.0/docs/plat/nxp/ |
| A D | nxp-layerscape.rst | 213 The following diagram is default DRAM0 memory layout in which secure memory is at top of DRAM0.
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| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | coding-guidelines.rst | 30 ``.checkpatch.conf`` file in the top-level directory.
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | firmware-design.rst | 147 to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
1709 data are relocated to the top of Trusted SRAM at runtime.
1714 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
1727 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
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