1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PMU_H 8 #define PMU_H 9 10 #include <soc.h> 11 12 struct rk3328_sleep_ddr_data { 13 uint32_t pmu_debug_enable; 14 uint32_t debug_iomux_save; 15 uint32_t pmic_sleep_save; 16 uint32_t pmu_wakeup_conf0; 17 uint32_t pmu_pwrmd_com; 18 uint32_t cru_mode_save; 19 uint32_t clk_sel0, clk_sel1, clk_sel18, 20 clk_sel20, clk_sel24, clk_sel38; 21 uint32_t clk_ungt_save[CRU_CLKGATE_NUMS]; 22 uint32_t cru_plls_con_save[MAX_PLL][CRU_PLL_CON_NUMS]; 23 }; 24 25 struct rk3328_sleep_sram_data { 26 uint32_t pmic_sleep_save; 27 uint32_t pmic_sleep_gpio_save[2]; 28 uint32_t ddr_grf_con0; 29 uint32_t dpll_con_save[CRU_PLL_CON_NUMS]; 30 uint32_t pd_sr_idle_save; 31 uint32_t uart2_ier; 32 }; 33 34 /***************************************************************************** 35 * The ways of cores power domain contorlling 36 *****************************************************************************/ 37 enum cores_pm_ctr_mode { 38 core_pwr_pd = 0, 39 core_pwr_wfi = 1, 40 core_pwr_wfi_int = 2 41 }; 42 43 enum pmu_cores_pm_by_wfi { 44 core_pm_en = 0, 45 core_pm_int_wakeup_en, 46 core_pm_dis_int, 47 core_pm_sft_wakeup_en 48 }; 49 50 extern void *pmu_cpuson_entrypoint_start; 51 extern void *pmu_cpuson_entrypoint_end; 52 53 #define CORES_PM_DISABLE 0x0 54 55 /***************************************************************************** 56 * pmu con,reg 57 *****************************************************************************/ 58 #define PMU_WAKEUP_CFG0 0x00 59 #define PMU_PWRDN_CON 0x0c 60 #define PMU_PWRDN_ST 0x10 61 #define PMU_PWRMD_COM 0x18 62 #define PMU_SFT_CON 0x1c 63 #define PMU_INT_CON 0x20 64 #define PMU_INT_ST 0x24 65 #define PMU_POWER_ST 0x44 66 #define PMU_CPUAPM_CON(n) (0x80 + (n) * 4) 67 #define PMU_SYS_REG(n) (0xa0 + (n) * 4) 68 69 #define CHECK_CPU_WFIE_BASE (GRF_BASE + GRF_CPU_STATUS(1)) 70 71 enum pmu_core_pwrst_shift { 72 clst_cpu_wfe = 0, 73 clst_cpu_wfi = 4, 74 }; 75 76 #define clstl_cpu_wfe (clst_cpu_wfe) 77 #define clstb_cpu_wfe (clst_cpu_wfe) 78 79 enum pmu_pd_id { 80 PD_CPU0 = 0, 81 PD_CPU1, 82 PD_CPU2, 83 PD_CPU3, 84 }; 85 86 enum pmu_power_mode_common { 87 pmu_mode_en = 0, 88 sref_enter_en, 89 global_int_disable_cfg, 90 cpu0_pd_en, 91 wait_wakeup_begin_cfg = 4, 92 l2_flush_en, 93 l2_idle_en, 94 ddrio_ret_de_req, 95 ddrio_ret_en = 8, 96 }; 97 98 enum pmu_sft_con { 99 upctl_c_sysreq_cfg = 0, 100 l2flushreq_req, 101 ddr_io_ret_cfg, 102 pmu_sft_ret_cfg, 103 }; 104 105 #define CKECK_WFE_MSK 0x1 106 #define CKECK_WFI_MSK 0x10 107 #define CKECK_WFEI_MSK 0x11 108 109 #define PD_CTR_LOOP 500 110 #define CHK_CPU_LOOP 500 111 #define MAX_WAIT_CONUT 1000 112 113 #define WAKEUP_INT_CLUSTER_EN 0x1 114 #define PMIC_SLEEP_REG 0x34 115 116 #define PLL_IS_NORM_MODE(mode, pll_id) \ 117 ((mode & (PLL_NORM_MODE(pll_id)) & 0xffff) != 0) 118 119 #define CTLR_ENABLE_G1_BIT BIT(1) 120 #define UART_FIFO_EMPTY BIT(6) 121 122 #define UART_IER 0x04 123 #define UART_FCR 0x08 124 #define UART_LSR 0x14 125 126 #define UART_INT_DISABLE 0x00 127 #define UART_FIFO_RESET 0x07 128 129 #endif /* PMU_H */ 130