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Searched refs:write_ctx_reg (Results 1 – 25 of 29) sorted by relevance

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/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dmce.c194 write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL)); in mce_command_handler()
195 write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL)); in mce_command_handler()
196 write_ctx_reg(gp_regs, CTX_GPREG_X6, (0ULL)); in mce_command_handler()
209 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); in mce_command_handler()
210 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64)); in mce_command_handler()
266 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); in mce_command_handler()
276 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); in mce_command_handler()
299 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64)); in mce_command_handler()
300 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); in mce_command_handler()
301 write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64)); in mce_command_handler()
[all …]
/arm-trusted-firmware-2.8.0/include/arch/aarch64/
A Dsmccc_helpers.h37 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \
41 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \
45 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
49 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \
53 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \
57 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \
61 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \
65 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \
76 write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v))
85 write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v))
/arm-trusted-firmware-2.8.0/services/std_svc/spm/spm_mm/
A Dspm_mm_setup.c74 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0, in spm_sp_setup()
125 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1, in spm_sp_setup()
128 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1, in spm_sp_setup()
131 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1, in spm_sp_setup()
171 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); in spm_sp_setup()
179 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1, in spm_sp_setup()
182 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1, in spm_sp_setup()
192 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CPACR_EL1, in spm_sp_setup()
A Dspm_mm_main.c207 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X0, smc_fid); in spm_mm_sp_call()
208 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X1, x1); in spm_mm_sp_call()
209 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X2, x2); in spm_mm_sp_call()
210 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X3, x3); in spm_mm_sp_call()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/
A Dplat_sip_calls.c68 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]); in plat_sip_handler()
69 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); in plat_sip_handler()
70 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]); in plat_sip_handler()
91 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, local_x1); in plat_sip_handler()
/arm-trusted-firmware-2.8.0/lib/extensions/sme/
A Dsme.c51 write_ctx_reg(state, CTX_CPTR_EL3, reg); in sme_enable()
56 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_enable()
103 write_ctx_reg(state, CTX_CPTR_EL3, reg); in sme_disable()
108 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_disable()
/arm-trusted-firmware-2.8.0/lib/extensions/sve/
A Dsve.c45 write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); in sve_enable()
48 write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, in sve_enable()
69 write_ctx_reg(state, CTX_CPTR_EL3, reg); in sve_disable()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/
A Dtegra_fiq_glue.c139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
140 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); in tegra_fiq_get_intr_context()
143 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); in tegra_fiq_get_intr_context()
146 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); in tegra_fiq_get_intr_context()
/arm-trusted-firmware-2.8.0/lib/el3_runtime/aarch64/
A Dcontext_mgmt.c146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); in setup_secure_context()
174 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); in setup_realm_context()
232 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); in setup_ns_context()
246 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, in setup_ns_context()
388 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); in setup_context_common()
389 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); in setup_context_common()
390 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); in setup_context_common()
1013 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); in cm_set_elr_el3()
1031 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); in cm_set_elr_spsr_el3()
1032 write_ctx_reg(state, CTX_SPSR_EL3, spsr); in cm_set_elr_spsr_el3()
[all …]
/arm-trusted-firmware-2.8.0/lib/el3_runtime/aarch32/
A Dcontext_mgmt.c104 write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr); in cm_setup_context()
119 write_ctx_reg(reg_ctx, CTX_SCR, scr); in cm_setup_context()
120 write_ctx_reg(reg_ctx, CTX_LR, ep->pc); in cm_setup_context()
121 write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr); in cm_setup_context()
/arm-trusted-firmware-2.8.0/services/spd/tlkd/
A Dtlkd_pm.c55 write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_SUSPEND); in cpu_suspend_handler()
88 write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_RESUME); in cpu_resume_handler()
A Dtlkd_main.c331 write_ctx_reg(gp_regs, CTX_GPREG_X4, (uint32_t)x2); in tlkd_smc_handler()
332 write_ctx_reg(gp_regs, CTX_GPREG_X5, (uint32_t)(x2 >> 32)); in tlkd_smc_handler()
333 write_ctx_reg(gp_regs, CTX_GPREG_X6, (uint32_t)x3); in tlkd_smc_handler()
334 write_ctx_reg(gp_regs, CTX_GPREG_X7, (uint32_t)(x3 >> 32)); in tlkd_smc_handler()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/
A Dplat_sip_calls.c116 write_ctx_reg(get_gpregs_ctx(handle), in plat_sip_handler()
145 write_ctx_reg(get_gpregs_ctx(handle), in plat_sip_handler()
147 write_ctx_reg(get_gpregs_ctx(handle), in plat_sip_handler()
/arm-trusted-firmware-2.8.0/services/std_svc/spmd/
A Dspmd_main.c104 write_ctx_reg(gpregs, CTX_GPREG_X1, in spmd_build_spmc_message()
107 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); in spmd_build_spmc_message()
108 write_ctx_reg(gpregs, CTX_GPREG_X3, message); in spmd_build_spmc_message()
220 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_INTERRUPT); in spmd_secure_interrupt_handler()
221 write_ctx_reg(gpregs, CTX_GPREG_X1, 0); in spmd_secure_interrupt_handler()
222 write_ctx_reg(gpregs, CTX_GPREG_X2, 0); in spmd_secure_interrupt_handler()
223 write_ctx_reg(gpregs, CTX_GPREG_X3, 0); in spmd_secure_interrupt_handler()
224 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); in spmd_secure_interrupt_handler()
225 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); in spmd_secure_interrupt_handler()
226 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); in spmd_secure_interrupt_handler()
[all …]
A Dspmd_pm.c91 write_ctx_reg(el3_state, CTX_ELR_EL3, entry_point); in spmd_cpu_on_finish_handler()
/arm-trusted-firmware-2.8.0/services/std_svc/spm/el3_spmc/
A Dspmc_pm.c29 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); in spmc_build_pm_message()
30 write_ctx_reg(gpregs, CTX_GPREG_X1, in spmc_build_pm_message()
33 write_ctx_reg(gpregs, CTX_GPREG_X2, FFA_FWK_MSG_BIT | in spmc_build_pm_message()
35 write_ctx_reg(gpregs, CTX_GPREG_X3, message); in spmc_build_pm_message()
/arm-trusted-firmware-2.8.0/include/lib/el3_runtime/aarch64/
A Dcontext.h401 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ macro
474 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
477 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
481 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
485 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
489 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
493 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
497 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
501 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
/arm-trusted-firmware-2.8.0/services/spd/opteed/
A Dopteed_main.c249 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), in opteed_smc_handler()
253 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), in opteed_smc_handler()
257 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), in opteed_smc_handler()
262 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), in opteed_smc_handler()
A Dopteed_pm.c71 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), CTX_GPREG_X0, in opteed_cpu_suspend_handler()
141 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), in opteed_cpu_suspend_finish_handler()
/arm-trusted-firmware-2.8.0/lib/extensions/sys_reg_trace/aarch64/
A Dsys_reg_trace.c35 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val); in sys_reg_trace_enable()
/arm-trusted-firmware-2.8.0/include/lib/el3_runtime/aarch32/
A Dcontext.h51 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[offset >> WORD_SHIFT]) \ macro
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t210/
A Dplat_sip_calls.c87 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, val); in plat_sip_handler()
/arm-trusted-firmware-2.8.0/services/std_svc/sdei/
A Dsdei_intr_mgmt.c195 write_ctx_reg(tgt_el3, CTX_SPSR_EL3, disp_ctx->spsr_el3); in restore_event_ctx()
196 write_ctx_reg(tgt_el3, CTX_ELR_EL3, disp_ctx->elr_el3); in restore_event_ctx()
203 write_ctx_reg(tgt_cve_2018_3639, CTX_CVE_2018_3639_DISABLE, in restore_event_ctx()
345 write_ctx_reg(tgt_cve_2018_3639, CTX_CVE_2018_3639_DISABLE, 0); in setup_ns_dispatch()
/arm-trusted-firmware-2.8.0/services/spd/tspd/
A Dtspd_pm.c160 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), in tspd_cpu_suspend_finish_handler()
/arm-trusted-firmware-2.8.0/lib/extensions/amu/aarch64/
A Damu.c85 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, value); in ctx_write_cptr_el3_tam()
95 write_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3, value); in ctx_write_scr_el3_amvoffen()

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