| /arm-trusted-firmware-2.8.0/plat/arm/board/rdn2/fdts/ |
| A D | rdn2_nt_fw_config.dts | 26 0x0 0x0
27 0x0 0x0
28 0x0 0x0
29 0x0 0x0
30 0x0 0x0
31 0x0 0x0
32 0x0 0x0
33 0x0 0x0
34 0x0 0x0
35 0x0 0x0
[all …]
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| /arm-trusted-firmware-2.8.0/lib/cpus/aarch64/ |
| A D | cortex_a78_ae.S | 37 cbz x0, 1f
41 bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
67 cbz x0, 1f
77 mov x0, #1
86 mov x0, #2
119 cbz x0, 1f
130 orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
156 cbz x0, 1f
165 orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
220 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
[all …]
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| A D | neoverse_v1.S | 41 cbz x0, 1f
44 ldr x0, =0x0
54 ldr x0, =0x1
64 ldr x0, =0x2
74 ldr x0, =0x3
116 cbz x0, 1f
144 cbz x0, 1f
172 cbz x0, 1f
200 cbz x0, 1f
231 cbz x0, 1f
[all …]
|
| A D | cortex_a78.S | 39 cbz x0, 1f
65 cbz x0, 1f
96 cbz x0, 1f
106 mov x0, #1
115 mov x0, #2
147 cbz x0, 1f
175 cbz x0, 1f
220 cbz x0, 1f
250 cbz x0, 1f
395 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
[all …]
|
| A D | cortex_a77.S | 43 cbz x0, 3f
48 cbz x0, 1f
49 ldr x0, =0x0
57 ldr x0, =0x1
65 ldr x0, =0x0
105 cbz x0, 1f
134 cbz x0, 1f
136 ldr x0,=0x4
185 cbz x0, 1f
213 cbz x0, 1f
[all …]
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| A D | neoverse_n2.S | 39 cbz x0, 1f
42 ldr x0,=0x6
50 ldr x0,=0x7
81 cbz x0, 1f
161 cbz x0, 1f
203 cbz x0, 1f
457 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
527 orr x0, x0, #TAM_BIT
532 orr x0, x0, #TAM_BIT
541 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
[all …]
|
| A D | cortex_a75.S | 32 cbz x0, 1f
60 cbz x0, 1f
81 mov x18, x0
84 mov x0, x18
89 mov x0, x18
96 msr vbar_el3, x0
111 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
127 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
133 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
204 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
[all …]
|
| A D | cortex_a72.S | 36 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
39 bic x0, x0, x1
51 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
64 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
74 mov x0, #1
92 cbz x0, 1f
166 mov x18, x0
169 mov x0, x18
198 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
209 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
[all …]
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| A D | cpu_helpers.S | 34 cmp x0, #0
67 cmp x0, x2
73 cmp x0, #0
374 ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
379 ldr x0, [x0, #CPU_EXTRA1_FUNC]
386 br x0
411 ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
416 ldr x0, [x0, #CPU_EXTRA2_FUNC]
440 ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
445 ldr x0, [x0, #CPU_EXTRA3_FUNC]
[all …]
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| A D | neoverse_n1.S | 42 cbz x0, 1f
45 ldr x0, =0x0
96 cbz x0, 1f
122 cbz x0, 1f
148 cbz x0, 1f
175 cbz x0, 1f
334 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
511 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
591 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
596 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
[all …]
|
| A D | cortex_x2.S | 41 cbz x0, 1f
43 ldr x0, =0x6
75 cbz x0, 1f
103 cbz x0, 1f
162 cbz x0, 1f
165 ldr x0, =0x3
173 ldr x0, =0x4
204 cbz x0, 1f
281 cbz x0, 1f
308 orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
[all …]
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| A D | cortex_a510.S | 35 cbz x0, 1f
65 cbz x0, 1f
95 cbz x0, 1f
126 cbz x0, 1f
129 mov x0, xzr
174 cbz x0, 1f
208 cbz x0, 1f
245 cbz x0, 1f
279 cbz x0, 1f
311 cbz x0, 1f
[all …]
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| A D | rainier.S | 63 cbz x0, 1f
85 orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2
90 mov x18, x0
93 mov x0, x18
99 mrs x0, actlr_el3
100 orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
101 msr actlr_el3, x0
104 mrs x0, actlr_el2
105 orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
127 orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK
[all …]
|
| /arm-trusted-firmware-2.8.0/include/arch/aarch64/ |
| A D | el3_common_macros.S | 39 orr x0, x0, x1
90 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT)
97 orr x0, x0, #SCR_EEL2_BIT
160 orr x0, x0, #MDCR_TTRF_BIT
235 orr x0, x0, #TTA_BIT
369 and x0, x0, #~(PAGE_SIZE_MASK)
451 add x0, x0, :lo12:__TEXT_START__
454 add x0, x0, :lo12:__RO_START__
458 add x0, x0, :lo12:__RW_START__
466 add x0, x0, :lo12:__NOBITS_START__
[all …]
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| A D | el2_common_macros.S | 40 mrs x0, sctlr_el2
41 orr x0, x0, x1
42 msr sctlr_el2, x0
77 orr x0, x0, #(HCR_API_BIT | HCR_APK_BIT)
79 msr hcr_el2, x0
159 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
163 msr DIT, x0
261 br x0
279 and x0, x0, #~(PAGE_SIZE_MASK)
343 add x0, x0, :lo12:__BSS_START__
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/aarch64/ |
| A D | tegra_helpers.S | 66 and x0, x0, x1
67 lsr x0, x0, #MIDR_PN_SHIFT
78 orr x0, x0, x1
85 orr x0, x0, x1
95 orr x0, x0, x1
99 orr x0, x0, x1
110 lsl x0, x1, x0
123 orr x0, x0, #EL0VCTEN_BIT
326 orr x0, x0, #1
335 bic x0, x0, #1
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/rpi/common/aarch64/ |
| A D | plat_helpers.S | 45 and x0, x0, #MPIDR_CLUSTER_MASK
46 add x0, x1, x0, LSR #6
59 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
80 lsl x0, x0, #3
82 add x0, x0, x2
89 str x1,[x0]
94 ldr x1, [x0]
100 ldr x1, [x0]
140 ldr x0, [x0]
143 csel x0, x0, xzr, eq
[all …]
|
| /arm-trusted-firmware-2.8.0/lib/extensions/mtpmu/aarch64/ |
| A D | mtpmu.S | 30 and x0, x1, x0, LSR #ID_AA64DFR0_MTPMU_SHIFT
32 cset x0, eq
46 lsr x1, x1, x0
48 cset x0, eq
67 cbz x0, 1f
70 mrs x0, mdcr_el3
72 bic x0, x0, x1
73 msr mdcr_el3, x0
90 mrs x0, mdcr_el2
92 bic x0, x0, x1
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/marvell/armada/common/aarch64/ |
| A D | marvell_helpers.S | 53 and x0, x0, #MPIDR_CLUSTER_MASK
54 add x0, x1, x0, LSR #7
71 mul x1, x0, x1
133 bic x0, x0, 0x1 /* M bit - MMU */
134 bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */
159 bic x0, x0, 0x1000 /* I bit - Icache L1 & L2 */
198 str w1, [x0]
217 mov x28, x0
245 mov x0, x28
246 br x0
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/arm/css/sgi/aarch64/ |
| A D | sgi_helper.S | 38 mov x4, x0
57 madd x0, x1, x4, x0
80 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
81 bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
82 msr CORTEX_A75_CPUPWRCTLR_EL1, x0
87 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
88 bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
89 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
94 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
95 bic x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/imx/common/ |
| A D | imx8_helpers.S | 32 mrs x0, midr_el1
33 ubfx x0, x0, MIDR_PN_SHIFT, #12
56 mrs x0, mpidr_el1
57 and x0, x0, #(MPIDR_CPU_MASK)
59 cset x0, eq
72 and x0, x0, #MPIDR_CLUSTER_MASK
73 add x0, x1, x0, LSR #6
84 and x0, x0, #MPIDR_CLUSTER_MASK
85 add x0, x1, x0, LSR #6
110 mov x0, #1
[all …]
|
| /arm-trusted-firmware-2.8.0/bl32/tsp/aarch64/ |
| A D | tsp_entrypoint.S | 35 ldp x0, x1, [x0, #SMC_ARG0]
67 and x0, x0, #~(PAGE_SIZE_MASK)
96 orr x0, x0, x1
97 bic x0, x0, #SCTLR_DSSBS_BIT
117 add x0, x0, :lo12:__TEXT_START__
120 add x0, x0, :lo12:__RO_START__
124 add x0, x0, :lo12:__RW_START__
138 add x0, x0, :lo12:__BSS_START__
146 add x0, x0, :lo12:__COHERENT_RAM_START__
197 mov x1, x0
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/ |
| A D | hisi_pwrc_sram.S | 19 mov x0, 0
20 msr oslar_el1, x0
23 bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \
25 orr x0, x0, #0x180000
26 orr x0, x0, #0xe000
38 mrs x0, mpidr_el1
39 and x1, x0, #MPIDR_CPU_MASK
40 and x0, x0, #MPIDR_CLUSTER_MASK
41 add x0, x1, x0, LSR #6
42 pen: ldr x4, [x3, x0, LSL #3]
[all …]
|
| /arm-trusted-firmware-2.8.0/lib/libc/aarch64/ |
| A D | setjmp.S | 20 stp x19, x20, [x0, #JMP_CTX_X19]
21 stp x21, x22, [x0, #JMP_CTX_X21]
22 stp x23, x24, [x0, #JMP_CTX_X23]
23 stp x25, x26, [x0, #JMP_CTX_X25]
24 stp x27, x28, [x0, #JMP_CTX_X27]
25 stp x29, x30, [x0, #JMP_CTX_X29]
26 stp x7, xzr, [x0, #JMP_CTX_SP]
28 mov x0, #0
37 ldp x7, xzr, [x0, #JMP_CTX_SP]
49 ldp x19, x20, [x0, #JMP_CTX_X19]
[all …]
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| /arm-trusted-firmware-2.8.0/bl2/aarch64/ |
| A D | bl2_entrypoint.S | 22 mov x20, x0
32 msr vbar_el1, x0
49 mrs x0, sctlr_el1
50 orr x0, x0, x1
51 bic x0, x0, #SCTLR_DSSBS_BIT
66 sub x1, x1, x0
76 add x0, x0, :lo12:__BSS_START__
79 sub x1, x1, x0
84 add x0, x0, :lo12:__COHERENT_RAM_START__
87 sub x1, x1, x0
[all …]
|