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/arm-trusted-firmware-2.8.0/plat/common/aarch64/
A Dcrash_console_helpers.S71 mrs x1, sctlr_el3
81 add x1, x1, :lo12:crash_console_triggered
82 ldarb w2, [x1]
87 stlrb w3, [x1]
112 add x1, x1, :lo12:crash_console_reg_stash
113 stp x14, x15, [x1]
132 mov x1, x15
137 mov x1, x15
146 add x1, x1, :lo12:crash_console_reg_stash
161 add x1, x1, :lo12:crash_console_reg_stash
[all …]
/arm-trusted-firmware-2.8.0/include/arch/aarch64/
A Dconsole_macros.S26 adrp x1, console_\_driver\()_putc
27 add x1, x1, :lo12:console_\_driver\()_putc
28 str x1, [x0, #CONSOLE_T_PUTC]
34 adrp x1, console_\_driver\()_getc
35 add x1, x1, :lo12:console_\_driver\()_getc
36 str x1, [x0, #CONSOLE_T_GETC]
42 adrp x1, console_\_driver\()_flush
43 add x1, x1, :lo12:console_\_driver\()_flush
44 str x1, [x0, #CONSOLE_T_FLUSH]
49 mov x1, #(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH)
[all …]
A Del3_common_macros.S371 add x1, x1, x0
461 add x1, x1, :lo12:__RW_END__
462 sub x1, x1, x0
468 add x1, x1, :lo12:__NOBITS_END__
469 sub x1, x1, x0
476 add x1, x1, :lo12:__BL2_NOLOAD_END__
477 sub x1, x1, x0
485 add x1, x1, :lo12:__BSS_END__
486 sub x1, x1, x0
494 sub x1, x1, x0
[all …]
/arm-trusted-firmware-2.8.0/bl2/aarch64/
A Dbl2_entrypoint.S23 mov x21, x1
50 orr x0, x0, x1
65 adr x1, __RW_END__
66 sub x1, x1, x0
77 adrp x1, __BSS_END__
78 add x1, x1, :lo12:__BSS_END__
79 sub x1, x1, x0
85 adrp x1, __COHERENT_RAM_END_UNALIGNED__
86 add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
87 sub x1, x1, x0
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/common/aarch64/
A Dboard_arm_helpers.S23 mrs x1, CurrentEl
24 lsr x1, x1, #MODE_EL_SHIFT
25 lsl x1, x1, #V2M_SYS_LED_EL_SHIFT
29 orr x0, x0, x1
30 mov x1, #V2M_SYSREGS_BASE
31 add x1, x1, #V2M_SYS_LED
32 str w0, [x1]
/arm-trusted-firmware-2.8.0/drivers/coreboot/cbmem_console/aarch64/
A Dcbmem_console.S38 str x0, [x1, #CONSOLE_T_BASE]
40 str w2, [x1, #CONSOLE_T_CBMC_SIZE]
41 mov x0, x1
56 ldr w2, [x1, #CONSOLE_T_CBMC_SIZE]
57 ldr x1, [x1, #CONSOLE_T_BASE]
58 add x1, x1, #8 /* keep address of body in x1 */
60 ldr w16, [x1, #-4] /* load cursor (one u32 before body) */
70 strb w0, [x1, w16, uxtw] /* body[cursor] = character */
80 str w16, [x1, #-4] /* write back cursor to memory */
94 ldr x1, [x0, #CONSOLE_T_CBMC_SIZE]
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/aarch64/
A Dlx2160a_warm_rst.S45 ldr x1, =NXP_DDR_ADDR
47 ldr w0, [x1, #SDRAM_CFG]
49 str w0, [x1, #SDRAM_CFG]
51 ldr w0, [x1, #DEBUG_2]
55 ldr w0, [x1, #DEBUG_26]
64 str w0, [x1, #DEBUG_26]
71 ldr w0, [x1, #DDR_DSR2]
73 str w0, [x1, #DDR_DSR2]
74 ldr w0, [x1, #DDR_DSR2]
98 ldr w0, [x1, #DDR_DSR2]
[all …]
A Dlx2160a.S297 lsl x1, x1, #8
330 orr x1, x1, #CPUECTLR_SMPEN_EN
336 bic x1, x1, #CPUECTLR_TIMER_MASK
427 orr x1, x1, #CNTP_CTL_EL0_IMASK
637 orr x1, x1, x2
641 orr x1, x1, x2
733 bic x1, x1, #CPUECTLR_RET_MASK
735 orr x1, x1, #CPUECTLR_SMPEN_EN
915 add x1, x1, #CCN_HNF_OFFSET
1358 bic x1, x1, x2
[all …]
/arm-trusted-firmware-2.8.0/lib/cpus/aarch64/
A Dcortex_a57.S21 mrs x1, sctlr_el3
22 bic x1, x1, #SCTLR_C_BIT
36 orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK
37 bic x0, x0, x1
90 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
97 mov x1, #0x00
132 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
204 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
231 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
258 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
[all …]
A Dcortex_a710.S68 mov x1, #0x20
129 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
155 orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
183 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
241 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
270 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
302 orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
334 orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
373 orr x1, x1, BIT(0)
402 orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36
[all …]
A Dcortex_a55.S37 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
45 mov x1, #0x00
67 orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
70 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
79 mov x1, #0x00
85 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3
86 cmp x1, #0
108 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
116 mov x1, #0x00
140 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
[all …]
A Dneoverse_n2.S65 mov x1, #0x00
83 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
109 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
136 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
207 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
264 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
292 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
329 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
358 orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
389 orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
[all …]
A Daem_generic.S16 mrs x1, sctlr_el3
17 bic x1, x1, #SCTLR_C_BIT
18 msr sctlr_el3, x1
27 mrs x1, clidr_el1
33 tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3)
64 mrs x1, sctlr_el3
65 bic x1, x1, #SCTLR_C_BIT
66 msr sctlr_el3, x1
A Dneoverse_n1.S60 mov x1, #0x10
98 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
124 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
150 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
151 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
177 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
203 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
229 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
255 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
307 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
[all …]
A Dcpu_helpers.S79 add x1, x1, x2, lsl #3
80 ldr x1, [x0, x1]
82 cmp x1, #0
85 br x1
196 add x1, x1, :lo12:unsupported_mpid_flag
247 cmp x0, x1
263 cmp x0, x1
279 cmp x0, x1
281 cbz x1, 1f
341 ldr x1, [x1, #CPU_ERRATA_PRINTED]
[all …]
/arm-trusted-firmware-2.8.0/services/spd/trusty/
A Dtrusty_helpers.S40 ldr x2, [x1]
41 ldr x3, [x1, #0x08]
42 ldr x4, [x1, #0x10]
59 push x8, xzr, x1
60 push xzr, xzr, x1
61 push xzr, xzr, x1
62 push xzr, xzr, x1
63 push xzr, xzr, x1
64 push xzr, xzr, x1
66 push xzr, x9, x1
[all …]
/arm-trusted-firmware-2.8.0/bl2u/aarch64/
A Dbl2u_entrypoint.S21 mov x20, x1
45 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
47 orr x0, x0, x1
62 adr x1, __RW_END__
63 sub x1, x1, x0
74 adrp x1, __BSS_END__
75 add x1, x1, :lo12:__BSS_END__
76 sub x1, x1, x0
104 mov x1, x21
/arm-trusted-firmware-2.8.0/plat/marvell/armada/common/
A Dmrvl_sip_svc.c74 u_register_t x1, in mrvl_sip_smc_handler() argument
82 u_register_t ret, read, x5 = x1; in mrvl_sip_smc_handler()
86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler()
90 if (!is_cp_range_valid(&x1)) { in mrvl_sip_smc_handler()
92 __func__, smc_fid, x1); in mrvl_sip_smc_handler()
96 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS; in mrvl_sip_smc_handler()
97 x1 += MVEBU_COMPHY_OFFSET; in mrvl_sip_smc_handler()
148 if (x1 >= MV_SIP_DFX_THERMAL_INIT && in mrvl_sip_smc_handler()
153 if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) { in mrvl_sip_smc_handler()
160 ret = mvebu_ddr_phy_write(x1, x2); in mrvl_sip_smc_handler()
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/aarch64/
A Dls1028a.S261 lsl x1, x1, #8
296 orr x1, x1, #CPUECTLR_SMPEN_EN
302 bic x1, x1, #CPUECTLR_TIMER_MASK
395 orr x1, x1, #CNTP_CTL_EL0_IMASK
614 orr x1, x1, x2
618 orr x1, x1, x2
708 bic x1, x1, #CPUECTLR_RET_MASK
710 orr x1, x1, #CPUECTLR_SMPEN_EN
792 bic x1, x1, #CPUECTLR_RET_MASK
1147 orr x1, x1, #0x4
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/css/common/aarch64/
A Dcss_helpers.S40 ldr x1, [x0]
41 cbz x1, 1f
42 br x1
78 and x1, x0, #MPIDR_CPU_MASK
81 add x0, x1, x0, LSR #6
99 mov x1, #0xffffffff
100 cmp x0, x1
112 mov_imm x1, SCP_BOOT_CFG_ADDR
113 ldr x1, [x1]
114 ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/
A Dplat_trampoline.S24 ldr x1, [x0]
28 cmp x1, x2
32 mov x1, #TEGRA194_STATE_SYSTEM_RESUME
33 lsl x1, x1, #16
35 add x1, x1, x2
36 str x1, [x0]
49 ldp x3, x4, [x1], #16
56 ldrb w3, [x1], #1
114 sub x0, x0, x1
128 sub x0, x0, x1
[all …]
/arm-trusted-firmware-2.8.0/lib/libc/aarch64/
A Dmemset.S35 aligned:cbz x1, x1_zero
38 bfi x1, x1, #32, #32
45 stp x1, x1, [x3], #16 /* write 64 bytes in a loop */
50 stp x1, x1, [x3], #16 /* write 32 bytes */
51 stp x1, x1, [x3], #16
53 stp x1, x1, [x3], #16 /* write 16 bytes */
55 str x1, [x3], #8 /* write 8 bytes */
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/aarch64/
A Dfvp_helpers.S41 mov_imm x1, PWRC_BASE
42 str w0, [x1, #PPOFFR_OFF]
58 ldr x1, [x0]
59 cbz x1, 1f
60 br x1
92 mov_imm x1, PWRC_BASE
93 str w2, [x1, #PSYSR_OFF]
94 ldr w2, [x1, #PSYSR_OFF]
136 and x0, x0, x1
173 madd x1, x2, x4, x1
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/common/
A Dimx_sip_svc.c20 u_register_t x1, in imx_sip_handler() argument
30 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
34 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
39 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
41 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
46 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
48 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
51 SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
54 return imx_otp_handler(smc_fid, handle, x1, x2); in imx_sip_handler()
60 SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle)); in imx_sip_handler()
[all …]
/arm-trusted-firmware-2.8.0/plat/rockchip/common/pmusram/
A Dcpus_on_fixed_addr.S27 ldr x1, =platform_cpu_warmboot
28 br x1
31 ldr x1, [x5, #PSRAM_DT_SP]
32 mov sp, x1
34 ldr x1, [x5, #PSRAM_DT_DDR_FUNC]
35 cmp x1, #0
37 blr x1
39 ldr x1, =bl31_warm_entrypoint
40 br x1

Completed in 43 milliseconds

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