| /arm-trusted-firmware-2.8.0/lib/romlib/templates/ |
| A D | wrapper.S | 8 ldr x17, =jmptbl
10 ldr x17, [x17]
11 add x16, x16, x17
|
| A D | wrapper_bti.S | 9 ldr x17, =jmptbl
11 ldr x17, [x17]
12 add x16, x16, x17
|
| /arm-trusted-firmware-2.8.0/lib/cpus/aarch64/ |
| A D | cortex_a510.S | 33 mov x17, x30
44 ret x17
74 ret x17
104 ret x17
146 ret x17
187 ret x17
224 ret x17
258 ret x17
290 ret x17
324 ret x17
[all …]
|
| A D | neoverse_n2.S | 60 ret x17
86 ret x17
182 ret x17
210 ret x17
239 ret x17
267 ret x17
304 ret x17
332 ret x17
361 ret x17
392 ret x17
[all …]
|
| A D | cortex_a710.S | 40 mov x17, x30
63 ret x17
106 ret x17
132 ret x17
186 ret x17
215 ret x17
244 ret x17
305 ret x17
347 ret x17
405 ret x17
[all …]
|
| A D | neoverse_n1.S | 55 ret x17
101 ret x17
127 ret x17
154 ret x17
180 ret x17
206 ret x17
232 ret x17
258 ret x17
284 ret x17
310 ret x17
[all …]
|
| A D | neoverse_v1.S | 96 ret x17
124 ret x17
152 ret x17
180 ret x17
208 ret x17
262 ret x17
299 ret x17
334 ret x17
363 ret x17
399 ret x17
[all …]
|
| A D | cortex_x2.S | 39 mov x17, x30
54 ret x17
73 mov x17, x30
83 ret x17
101 mov x17, x30
111 ret x17
140 ret x17
183 ret x17
222 ret x17
260 ret x17
[all …]
|
| A D | cortex_a78.S | 37 mov x17, x30
45 ret x17
63 mov x17, x30
73 ret x17
126 ret x17
155 ret x17
199 ret x17
228 ret x17
263 ret x17
292 ret x17
[all …]
|
| A D | cortex_a57.S | 86 mov x17, x30
93 ret x17
135 ret x17
163 ret x17
207 ret x17
234 ret x17
261 ret x17
295 ret x17
322 ret x17
349 ret x17
[all …]
|
| A D | cortex_a55.S | 33 mov x17, x30
41 ret x17
63 mov x17, x30
74 ret x17
104 mov x17, x30
112 ret x17
136 mov x17, x30
144 ret x17
164 mov x17, x30
172 ret x17
[all …]
|
| A D | cortex_a77.S | 41 mov x17, x30
80 ret x17
103 mov x17, x30
113 ret x17
132 mov x17, x30
165 ret x17
183 mov x17, x30
193 ret x17
221 ret x17
245 ret x17
[all …]
|
| A D | cortex_a78c.S | 31 mov x17, x30
39 ret x17
60 mov x17, x30
69 ret x17
94 mov x17, x30
110 ret x17
130 mov x17, x30
145 ret x17
|
| A D | dsu_helpers.S | 51 mov x17, x30
61 ret x17
129 mov x17, x30
140 ret x17
183 mov x17, x30
193 ret x17
|
| A D | cortex_x1.S | 36 mov x17, x30
44 ret x17
63 mov x17, x30
72 ret x17
91 mov x17, x30
100 ret x17
|
| A D | cortex_a78_ae.S | 35 mov x17, x30
45 ret x17
65 mov x17, x30
97 ret x17
117 mov x17, x30
134 ret x17
154 mov x17, x30
169 ret x17
|
| A D | cortex_a76.S | 313 mov x17, x30
321 ret x17
341 mov x17, x30
349 ret x17
377 ret x17
405 ret x17
433 ret x17
476 ret x17
516 ret x17
579 ret x17
[all …]
|
| /arm-trusted-firmware-2.8.0/plat/amlogic/common/include/ |
| A D | plat_macros.S | 36 mov_imm x17, AML_GICC_BASE
39 ldr w8, [x17, #GICC_HPPIR]
40 ldr w9, [x17, #GICC_AHPPIR]
41 ldr w10, [x17, #GICC_CTLR]
|
| /arm-trusted-firmware-2.8.0/plat/renesas/common/include/ |
| A D | plat_macros.S | 31 mov_imm x17, RCAR_GICC_BASE
37 ldr w8, [x17, #GICC_HPPIR]
38 ldr w9, [x17, #GICC_AHPPIR]
39 ldr w10, [x17, #GICC_CTLR]
|
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/include/ |
| A D | plat_macros.S | 36 mov_imm x17, BASE_GICC_BASE
40 ldr w8, [x17, #GICC_HPPIR]
41 ldr w9, [x17, #GICC_AHPPIR]
42 ldr w10, [x17, #GICC_CTLR]
|
| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/include/ |
| A D | plat_macros.S | 37 mov_imm x17, PLAT_ARM_GICC_BASE
42 ldr w8, [x17, #GICC_HPPIR]
43 ldr w9, [x17, #GICC_AHPPIR]
44 ldr w10, [x17, #GICC_CTLR]
|
| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/include/ |
| A D | plat_macros.S | 37 mov_imm x17, GICC_REG_BASE
42 ldr w8, [x17, #GICC_HPPIR]
43 ldr w9, [x17, #GICC_AHPPIR]
44 ldr w10, [x17, #GICC_CTLR]
|
| /arm-trusted-firmware-2.8.0/plat/xilinx/versal/include/ |
| A D | plat_macros.S | 67 ldr w8, [x17, #GICC_HPPIR]
68 ldr w9, [x17, #GICC_AHPPIR]
69 ldr w10, [x17, #GICC_CTLR]
105 mov_imm x17, PLAT_VERSAL_GICD_BASE
|
| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/include/ |
| A D | plat_macros.S | 32 mov_imm x17, BASE_GICC_BASE
36 mov_imm x17, VE_GICC_BASE
|
| /arm-trusted-firmware-2.8.0/plat/xilinx/versal_net/include/ |
| A D | plat_macros.S | 69 ldr w8, [x17, #GICC_HPPIR]
70 ldr w9, [x17, #GICC_AHPPIR]
71 ldr w10, [x17, #GICC_CTLR]
|