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Searched refs:x3 (Results 1 – 25 of 209) sorted by relevance

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/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/
A Dhisi_pwrc_sram.S29 mrs x3, actlr_el3
30 orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
31 msr actlr_el3, x3
33 mrs x3, actlr_el2
34 orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT
35 msr actlr_el2, x3
37 ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD
42 pen: ldr x4, [x3, x0, LSL #3]
48 mov x3, #0x0
/arm-trusted-firmware-2.8.0/lib/libc/aarch64/
A Dmemset.S22 mov x3, x0 /* keep x0 */
28 strb w1, [x3], #1
31 tst x3, #7
45 stp x1, x1, [x3], #16 /* write 64 bytes in a loop */
50 stp x1, x1, [x3], #16 /* write 32 bytes */
51 stp x1, x1, [x3], #16
53 stp x1, x1, [x3], #16 /* write 16 bytes */
55 str x1, [x3], #8 /* write 8 bytes */
57 str w1, [x3], #4 /* write 4 bytes */
59 strh w1, [x3], #2 /* write 2 bytes */
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/common/
A Dimx_sip_svc.c22 u_register_t x3, in imx_sip_handler() argument
30 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
34 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
39 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
41 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
46 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
48 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
51 SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
60 SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle)); in imx_sip_handler()
65 SMC_RET1(handle, imx_hab_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
[all …]
A Dimx_sip_handler.c42 u_register_t x3, in imx_srtc_handler() argument
49 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
73 u_register_t x3) in imx_cpufreq_handler() argument
77 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
96 u_register_t x3) in imx_wakeup_src_handler() argument
141 u_register_t x3, in imx_misc_set_temp_handler() argument
153 u_register_t x3, in imx_src_handler() argument
181 u_register_t x3, in imx_get_commit_hash() argument
207 u_register_t x3, in imx_buildinfo_handler() argument
226 u_register_t x3, in imx_kernel_entry_handler() argument
[all …]
/arm-trusted-firmware-2.8.0/plat/imx/common/include/
A Dimx_sip_svc.h53 u_register_t x2, u_register_t x3,
57 u_register_t x2, u_register_t x3);
61 u_register_t x1, u_register_t x2, u_register_t x3);
64 u_register_t x2, u_register_t x3);
69 u_register_t x2, u_register_t x3, void *handle);
74 u_register_t x2, u_register_t x3, u_register_t x4);
79 u_register_t x2, u_register_t x3);
81 u_register_t x2, u_register_t x3, u_register_t x4);
83 u_register_t x2, u_register_t x3);
87 u_register_t x2, u_register_t x3,
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/tc/include/
A Dtc_helpers.S36 lsl x3, x0, #MPIDR_AFFINITY_BITS
37 csel x3, x3, x0, eq
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/aarch64/
A Dls1028a.S151 mov x3, x30
163 mov x30, x3
176 mov x3, x30
197 mov x30, x3
367 orr x3, x3, #OSDLR_EL1_DLK_LOCK
422 cmp x2, x3
486 bic x3, x3, #OSDLR_EL1_DLK_LOCK
1022 lsl x3, x3, x0
1034 lsr x3, x3, #1
1079 lsl x3, x3, x0
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/common/aarch64/
A Dbl31_data.S161 clz x3, x0
174 add x3, x3, x1
185 mul x3, x3, x0
200 sub x3, x3, x1
208 dc cvac, x3
224 clz x3, x0
237 add x3, x3, x2
248 mul x3, x3, x0
263 sub x3, x3, x2
434 mov x3, #2
[all …]
/arm-trusted-firmware-2.8.0/services/std_svc/
A Dstd_svc_setup.c98 u_register_t x3, in std_svc_smc_handler() argument
109 x3 &= UINT32_MAX; in std_svc_smc_handler()
132 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
150 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
161 return spmd_ffa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
168 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
175 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
183 return rmmd_rmm_el3_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
188 return rmmd_rmi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
195 return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
[all …]
A Dpci_svc.c44 u_register_t x3, in pci_smc_handler() argument
73 if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) { in pci_smc_handler()
79 if (pci_read_config(x1, x2, x3, &ret) != 0U) { in pci_smc_handler()
89 if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) { in pci_smc_handler()
92 ret = pci_write_config(x1, x2, x3, x4); in pci_smc_handler()
101 if ((x2 != 0U) || (x3 != 0U) || (x4 != 0U)) { in pci_smc_handler()
/arm-trusted-firmware-2.8.0/lib/pmf/
A Dpmf_smc.c20 u_register_t x3, in pmf_smc_handler() argument
33 x3 = (uint32_t)x3; in pmf_smc_handler()
43 (unsigned int)x3, &ts_value); in pmf_smc_handler()
56 (unsigned int)x3, &ts_value); in pmf_smc_handler()
/arm-trusted-firmware-2.8.0/plat/arm/board/arm_fpga/aarch64/
A Dfpga_helpers.S80 ldr x3, [x1, x0, LSL #PLAT_FPGA_HOLD_ENTRY_SHIFT]
81 cmp x3, #PLAT_FPGA_HOLD_STATE_GO
86 ldr x3, [x2]
87 br x3
136 lsl x3, x0, #MPIDR_AFFINITY_BITS
137 csel x3, x3, x0, eq
140 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
141 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
142 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/arm-trusted-firmware-2.8.0/plat/mediatek/common/
A Dmtk_sip_svc.c28 u_register_t x3, in mediatek_plat_sip_handler() argument
43 u_register_t x3, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
94 u_register_t x3, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/arm-trusted-firmware-2.8.0/lib/aarch64/
A Dcache_helpers.S28 sub x3, x2, #1
29 bic x0, x0, x3
42 mov x3, x30
45 mov x30, x3
100 sub x3, x2, #1
101 bic x0, x0, x3
132 lsl x3, x3, \ls
138 cbz x3, exit
204 cmp x3, x10
237 mov x3, \level
[all …]
A Dmisc_helpers.S392 orr x3, x0, x1
393 tst x3, #0xf
529 1: ldr x3, [x1]
532 cmp x3, x6
536 cmp x3, x7
538 add x3, x3, x0
539 str x3, [x1]
569 1: ldr x3, [x1, #8]
570 cbz x3, 2f
578 add x3, x0, x3
[all …]
/arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/aarch64/
A Dls1088a.S173 mov x3, x30
184 mov x30, x3
216 mov x3, x30
410 orr x3, x3, #OSDLR_EL1_DLK_LOCK
529 bic x3, x3, #OSDLR_EL1_DLK_LOCK
892 lsl x3, x3, x0
893 sub x3, x3, #2
1247 lsl x3, x3, x0
1259 lsr x3, x3, #1
1287 lsl x3, x3, x0
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/
A Dplat_sip_calls.c19 u_register_t x3, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
35 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
40 ret = msdc_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/
A Dplat_sip_calls.c18 u_register_t x3, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
35 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); in mediatek_plat_sip_handler()
40 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/
A Dplat_sip_calls.c20 u_register_t x3, in mediatek_plat_sip_handler() argument
37 ret = spm_vcorefs_v2_args(x1, x2, x3, &x4); in mediatek_plat_sip_handler()
42 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
47 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &ret_val); in mediatek_plat_sip_handler()
/arm-trusted-firmware-2.8.0/plat/arm/common/
A Darm_sip_svc.c46 u_register_t x3, in arm_sip_handler() argument
61 return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
70 return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
79 return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
97 (uint32_t) x1, (uint32_t) x2, (uint32_t) x3, in arm_sip_handler()
/arm-trusted-firmware-2.8.0/bl31/aarch64/
A Dea_delegate.S68 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
111 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
177 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
178 cmp x3, #SYNC_EA_FSC
220 ubfx x3, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH
221 cmp x3, #ERROR_STATUS_UET_UC
251 mrs x3, elr_el3
252 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
272 mov x3, sp
307 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
[all …]
/arm-trusted-firmware-2.8.0/plat/intel/soc/common/
A Dsocfpga_sip_svc.c42 uint64_t x3, in socfpga_sip_handler() argument
641 u_register_t x3, in sip_smc_handler_v1() argument
716 (uint32_t)x3, &retval); in sip_smc_handler_v1()
815 if (x3 == FCS_MODE_DECRYPT) { in sip_smc_handler_v1()
818 } else if (x3 == FCS_MODE_ENCRYPT) { in sip_smc_handler_v1()
882 (uint32_t *) &x3, &mbox_error); in sip_smc_handler_v1()
972 x3, x4, x5, (uint32_t *) &x6, false, in sip_smc_handler_v1()
980 x3, x4, x5, (uint32_t *) &x6, true, in sip_smc_handler_v1()
1021 x1, x2, x3, x4, x5, (uint32_t *) &x6, in sip_smc_handler_v1()
1030 x1, x2, x3, x4, x5, (uint32_t *) &x6, in sip_smc_handler_v1()
[all …]
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/aarch64/
A Dfvp_helpers.S163 lsl x3, x0, #MPIDR_AFFINITY_BITS
164 csel x3, x3, x0, eq
167 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
168 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
169 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/
A Dplat_trampoline.S49 ldp x3, x4, [x1], #16
50 stp x3, x4, [x0], #16
135 mov x3, #MC_SECURITY_CFG3_0
136 ldr w1, [x0, x3]
138 mov x3, #MC_SECURITY_CFG0_0
139 ldr w2, [x0, x3]
140 orr x3, x1, x2 /* TZDRAM base */
147 str x0, [x3, x2] /* set value in TZDRAM */
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/
A Dimx_hab.c91 u_register_t x3, in imx_hab_handler() argument
101 (const void *)x3, (size_t)x4); in imx_hab_handler()
104 x2, (void **)x3, (size_t *)x4, NULL); in imx_hab_handler()
107 (uint32_t)x2, (uint8_t *)x3, (size_t *)x4); in imx_hab_handler()
110 (enum hab_state *)x3); in imx_hab_handler()
116 HAB_CID_ATF, x2, (void **)x3, (size_t *)x4, NULL); in imx_hab_handler()

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