1 /*****************************************************************************/
2 /**
3  * \file
4  * \brief   UTCB definitions for X86.
5  * \ingroup  l4_utcb_api
6  */
7 /*
8  * (c) 2008-2009 Adam Lackorzynski <adam@os.inf.tu-dresden.de>,
9  *               Alexander Warg <warg@os.inf.tu-dresden.de>
10  *     economic rights: Technische Universität Dresden (Germany)
11  *
12  * This file is part of TUD:OS and distributed under the terms of the
13  * GNU General Public License 2.
14  * Please see the COPYING-GPL-2 file for details.
15  *
16  * As a special exception, you may use this file as part of a free software
17  * library without restriction.  Specifically, if other files instantiate
18  * templates or use macros or inline functions from this file, or you compile
19  * this file and link it with other files to produce an executable, this
20  * file does not by itself cause the resulting executable to be covered by
21  * the GNU General Public License.  This exception does not however
22  * invalidate any other reasons why the executable file might be covered by
23  * the GNU General Public License.
24  */
25 /*****************************************************************************/
26 #ifndef __L4_SYS__INCLUDE__ARCH_X86__UTCB_H__
27 #define __L4_SYS__INCLUDE__ARCH_X86__UTCB_H__
28 
29 #include <l4/sys/types.h>
30 
31 /**
32  * \defgroup l4_utcb_api_x86 x86 Virtual Registers (UTCB)
33  * \ingroup  l4_utcb_api
34  */
35 
36 /**
37  * \brief UTCB constants for x86
38  * \ingroup l4_utcb_api_x86
39  * \hideinitializer
40  */
41 enum L4_utcb_consts_x86
42 {
43   /// Number if message registers used for exception IPC
44   L4_UTCB_EXCEPTION_REGS_SIZE    = 19,
45 
46   /// Total number of message register (MRs) available
47   L4_UTCB_GENERIC_DATA_SIZE      = 63,
48 
49   /// Total number of buffer registers (BRs) available
50   L4_UTCB_GENERIC_BUFFERS_SIZE   = 58,
51 
52   /// Offset of MR[0] relative to the UTCB pointer
53   L4_UTCB_MSG_REGS_OFFSET        = 0,
54 
55   /// Offset of BR[0] relative to the UTCB pointer
56   L4_UTCB_BUF_REGS_OFFSET        = 64 * sizeof(l4_umword_t),
57 
58   /// Offset of TCR[0] relative to the UTCB pointer
59   L4_UTCB_THREAD_REGS_OFFSET     = 123 * sizeof(l4_umword_t),
60 
61   /// BDR flag to accept reception of FPU state
62   L4_UTCB_INHERIT_FPU            = 1UL << 24,
63 
64   /// Offset of two consecutive UTCBs
65   L4_UTCB_OFFSET                 = 512,
66 };
67 
68 /**
69  * \brief UTCB structure for exceptions.
70  * \ingroup l4_utcb_api_x86
71  */
72 typedef struct l4_exc_regs_t
73 {
74   l4_umword_t es;      /**< es register */
75   l4_umword_t ds;      /**< ds register */
76   l4_umword_t gs;      /**< gs register */
77   l4_umword_t fs;      /**< fs register */
78 
79   l4_umword_t edi;     /**< edi register */
80   l4_umword_t esi;     /**< esi register */
81   l4_umword_t ebp;     /**< ebp register */
82   l4_umword_t pfa;     /**< page fault address */
83   l4_umword_t ebx;     /**< ebx register */
84   l4_umword_t edx;     /**< edx register */
85   l4_umword_t ecx;     /**< ecx register */
86   l4_umword_t eax;     /**< eax register */
87 
88   l4_umword_t trapno;  /**< trap number */
89   l4_umword_t err;     /**< error code */
90 
91   l4_umword_t ip;     /**< instruction pointer */
92   l4_umword_t dummy1;  /**< dummy \internal */
93   l4_umword_t flags;  /**< eflags */
94   l4_umword_t sp;     /**< stack pointer */
95   l4_umword_t ss;     /**< ss register */
96 } l4_exc_regs_t;
97 
98 #include_next <l4/sys/utcb.h>
99 
100 /*
101  * ==================================================================
102  * Implementations.
103  */
104 
l4_utcb_direct(void)105 L4_INLINE l4_utcb_t *l4_utcb_direct(void) L4_NOTHROW
106 {
107   l4_utcb_t *utcb;
108   __asm__ ("mov %%fs:0, %0" : "=r" (utcb));
109   return utcb;
110 }
111 
l4_utcb_exc_pc(l4_exc_regs_t const * u)112 L4_INLINE l4_umword_t l4_utcb_exc_pc(l4_exc_regs_t const *u) L4_NOTHROW
113 {
114   return u->ip;
115 }
116 
l4_utcb_exc_pc_set(l4_exc_regs_t * u,l4_addr_t pc)117 L4_INLINE void l4_utcb_exc_pc_set(l4_exc_regs_t *u, l4_addr_t pc) L4_NOTHROW
118 {
119   u->ip = pc;
120 }
121 
l4_utcb_exc_sp_set(l4_exc_regs_t * u,l4_addr_t sp)122 L4_INLINE void l4_utcb_exc_sp_set(l4_exc_regs_t *u, l4_addr_t sp) L4_NOTHROW
123 {
124   u->sp = sp;
125 }
126 
l4_utcb_exc_typeval(l4_exc_regs_t const * u)127 L4_INLINE l4_umword_t l4_utcb_exc_typeval(l4_exc_regs_t const *u) L4_NOTHROW
128 {
129   return u->trapno;
130 }
131 
l4_utcb_exc_is_pf(l4_exc_regs_t const * u)132 L4_INLINE int l4_utcb_exc_is_pf(l4_exc_regs_t const *u) L4_NOTHROW
133 {
134   return u->trapno == 14;
135 }
136 
l4_utcb_exc_pfa(l4_exc_regs_t const * u)137 L4_INLINE l4_addr_t l4_utcb_exc_pfa(l4_exc_regs_t const *u) L4_NOTHROW
138 {
139   return (u->pfa & ~7UL) | (u->err & 2);
140 }
141 
l4_utcb_exc_is_ex_regs_exception(l4_exc_regs_t const * u)142 L4_INLINE int l4_utcb_exc_is_ex_regs_exception(l4_exc_regs_t const *u) L4_NOTHROW
143 {
144   return l4_utcb_exc_typeval(u) == 0xff;
145 }
146 
147 #endif /* ! __L4_SYS__INCLUDE__ARCH_X86__UTCB_H__ */
148