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Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 38) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_irq.c693 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()
724 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()
778 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_outbox_irq_state()
804 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_trace_irq_state()
/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dmxgpu_nv.c266 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()
332 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
A Dmxgpu_ai.c246 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()
306 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
A Damdgpu_irq.h43 AMDGPU_IRQ_STATE_ENABLE, enumerator
A Dmxgpu_vi.c507 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()
545 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
A Dnbio_v7_4.c465 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()
510 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
A Dsi_dma.c602 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
618 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
A Damdgpu_irq.c506 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
A Dvce_v2_0.c554 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
A Dsdma_v2_4.c1012 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1028 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
A Dcik_sdma.c1119 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1135 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
A Dsdma_v3_0.c1346 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
1362 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
A Dgmc_v9_0.c443 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()
509 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
A Dgmc_v6_0.c1046 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
A Dgfx_v9_0.c5597 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
5600 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()
5649 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
5667 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()
5670 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
5686 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()
5689 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
5721 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_cp_ecc_error_state()
A Dgfx_v6_0.c3209 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3238 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3272 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()
3297 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
A Dvce_v3_0.c736 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
A Dgmc_v11_0.c75 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v11_0_vm_fault_interrupt_state()
A Dgfx_v11_0.c5802 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()
5859 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_compute_eop_interrupt_state()
5889 ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0; in gfx_v11_0_set_cp_ecc_error_state()
5994 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_reg_fault_state()
5997 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6013 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_inst_fault_state()
6016 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
A Dgfx_v7_0.c4671 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()
4722 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_compute_eop_interrupt_state()
4745 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_reg_fault_state()
4770 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_inst_fault_state()
A Dgmc_v10_0.c89 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
A Ddce_v8_0.c2927 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()
2978 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vline_interrupt_state()
3006 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_hpd_interrupt_state()
A Ddce_v10_0.c3011 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()
3040 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vline_interrupt_state()
3069 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_hpd_irq_state()
A Dgmc_v7_0.c1243 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v7_0_vm_fault_interrupt_state()
A Dvce_v4_0.c1050 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v4_0_set_interrupt_state()

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