Searched refs:B0_R1_CSR (Results 1 – 5 of 5) sorted by relevance
276 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R1_CSR) ; in init_rx()968 outpd(ADDR(B0_R1_CSR),CSR_SET_RESET) ; in init_mac()972 outpd(ADDR(B0_R1_CSR),CSR_CLR_RESET) ; in init_mac()
575 outpd(ADDR(B0_R1_CSR),CSR_START) ; in mac_drv_repair_descr()1425 outpd(ADDR(B0_R1_CSR),CSR_START) ; in hwm_rx_frag()
81 #define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */ macro
36 B0_R1_CSR = 0x0060, enumerator
3309 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); in skge_error_irq()
Completed in 27 milliseconds