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/linux-6.3-rc2/drivers/clk/stm32/
A Dstm32mp13_rcc.h339 #define RCC_BDCR_LSEON BIT(0)
340 #define RCC_BDCR_LSEBYP BIT(1)
341 #define RCC_BDCR_LSERDY BIT(2)
342 #define RCC_BDCR_DIGBYP BIT(3)
344 #define RCC_BDCR_LSECSSON BIT(8)
345 #define RCC_BDCR_LSECSSD BIT(9)
347 #define RCC_BDCR_RTCCKEN BIT(20)
442 #define RCC_PLL1CR_PLLON BIT(0)
478 #define RCC_PLL2CR_PLLON BIT(0)
514 #define RCC_PLL3CR_PLLON BIT(0)
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/linux-6.3-rc2/include/linux/soc/mediatek/
A Dinfracfg.h43 #define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
45 #define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4))
120 BIT(10) | BIT(12) | \
121 BIT(14) | BIT(16) | \
122 BIT(24) | BIT(26))
125 BIT(15) | BIT(17) | \
126 BIT(25) | BIT(27))
175 #define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30))
193 #define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11))
335 BIT(9) | BIT(13))
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/linux-6.3-rc2/drivers/platform/x86/intel/pmc/
A Dadl.c16 {"XHCI", BIT(3)},
17 {"SPA", BIT(4)},
18 {"SPB", BIT(5)},
19 {"SPC", BIT(6)},
20 {"GBE", BIT(7)},
22 {"SATA", BIT(0)},
27 {"SPD", BIT(5)},
28 {"LPSS", BIT(6)},
30 {"SMB", BIT(0)},
31 {"ISH", BIT(1)},
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A Dcnp.c40 {"SBR8", BIT(7)},
75 {"SPF", BIT(6)},
83 {"PSF6", BIT(5)},
84 {"PSF7", BIT(6)},
85 {"PSF8", BIT(7)},
100 {"OTG_D3", BIT(1)},
101 {"XHCI_D3", BIT(2)},
102 {"LPIO_D3", BIT(3)},
103 {"SDX_D3", BIT(4)},
104 {"SATA_D3", BIT(5)},
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A Dtgl.c17 {"PSF9", BIT(0)},
18 {"RES_66", BIT(1)},
19 {"RES_67", BIT(2)},
20 {"RES_68", BIT(3)},
21 {"RES_69", BIT(4)},
22 {"RES_70", BIT(5)},
23 {"TBTLSX", BIT(6)},
58 {"OTG_PG_STS", BIT(5)},
59 {"SPA_PG_STS", BIT(6)},
60 {"SPB_PG_STS", BIT(7)},
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/linux-6.3-rc2/drivers/gpu/drm/bridge/
A Dsil-sii8620.h46 #define BIT_DPD_PWRON_PLL BIT(7)
47 #define BIT_DPD_PDNTX12 BIT(6)
48 #define BIT_DPD_PDNRX12 BIT(5)
49 #define BIT_DPD_OSC_EN BIT(4)
50 #define BIT_DPD_PWRON_HSIC BIT(3)
51 #define BIT_DPD_PDIDCK_N BIT(2)
60 #define BIT_DCTL_TRANSCODE BIT(3)
149 #define BIT_DDC_CMD_DONE BIT(3)
219 #define BIT_BIST_TRANS BIT(2)
220 #define BIT_BIST_RESET BIT(1)
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/linux-6.3-rc2/drivers/net/ethernet/freescale/dpaa2/
A Ddpkg.h64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
67 #define NH_FLD_ETH_TYPE BIT(3)
73 #define NH_FLD_VLAN_VPRI BIT(0)
85 #define NH_FLD_IP_VER BIT(0)
86 #define NH_FLD_IP_DSCP BIT(2)
87 #define NH_FLD_IP_ECN BIT(3)
89 #define NH_FLD_IP_SRC BIT(5)
90 #define NH_FLD_IP_DST BIT(6)
92 #define NH_FLD_IP_ID BIT(8)
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/linux-6.3-rc2/drivers/net/wireless/realtek/rtl8xxxu/
A Drtl8xxxu_regs.h123 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
290 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
305 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
308 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
326 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
327 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
328 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
345 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
785 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
984 #define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27))
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/linux-6.3-rc2/drivers/staging/emxx_udc/
A Demxx_udc.h48 #define TEST_FORCE_ENABLE (BIT(18) | BIT(16))
76 #define UFRAME (BIT(14) | BIT(13) | BIT(12))
82 #define SQUSET (BIT(7) | BIT(6) | BIT(5) | BIT(4))
84 #define USB_SQUSET (BIT(6) | BIT(5) | BIT(4))
156 #define EP0_DW (BIT(6) | BIT(5))
158 #define EP0_DW3 (BIT(6) | BIT(5))
189 #define EP0_STATUS_RW_BIT (BIT(16) | BIT(15) | BIT(11) | 0xFF)
221 #define EPN_MODE (BIT(25) | BIT(24))
234 #define EPN_DW (BIT(6) | BIT(5))
236 #define EPN_DW3 (BIT(6) | BIT(5))
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/linux-6.3-rc2/drivers/gpu/drm/mcde/
A Dmcde_dsi_regs.h8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
66 #define DSI_MCTL_MAIN_EN_DAT1_EN BIT(4)
67 #define DSI_MCTL_MAIN_EN_DAT2_EN BIT(5)
71 #define DSI_MCTL_MAIN_EN_IF1_EN BIT(9)
72 #define DSI_MCTL_MAIN_EN_IF2_EN BIT(10)
182 #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS (BIT(12) | BIT(13))
189 #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 (BIT(17) | BIT(18))
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/linux-6.3-rc2/drivers/staging/sm750fb/
A Dddk750_reg.h7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
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/linux-6.3-rc2/arch/mips/include/asm/mach-ath79/
A Dar71xx_regs.h555 #define MISC_INT_ETHSW BIT(12)
557 #define MISC_INT_TIMER3 BIT(9)
558 #define MISC_INT_TIMER2 BIT(8)
559 #define MISC_INT_DMA BIT(7)
560 #define MISC_INT_OHCI BIT(6)
561 #define MISC_INT_PERFC BIT(5)
562 #define MISC_INT_WDOG BIT(4)
563 #define MISC_INT_UART BIT(3)
564 #define MISC_INT_GPIO BIT(2)
565 #define MISC_INT_ERROR BIT(1)
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/linux-6.3-rc2/drivers/net/wireless/realtek/rtw89/
A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
15 #define B_AX_ISO_EB2CORE BIT(8)
19 #define B_AX_FEN_BBRSTB BIT(0)
25 #define B_AX_EN_WLON BIT(16)
53 #define B_AX_EF_RDT BIT(27)
57 #define B_AX_EF_POR BIT(10)
62 #define B_AX_EF_RDY BIT(29)
68 #define B_AX_EF_ENT BIT(31)
83 #define B_AX_ENHTP BIT(14)
85 #define B_AX_ENSIC BIT(12)
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/linux-6.3-rc2/drivers/usb/dwc2/
A Dhw.h14 #define GOTGCTL_CHIRPEN BIT(27)
18 #define GOTGCTL_OTGVER BIT(20)
19 #define GOTGCTL_BSESVLD BIT(19)
20 #define GOTGCTL_ASESVLD BIT(18)
22 #define GOTGCTL_CONID_B BIT(16)
26 #define GOTGCTL_HNPREQ BIT(9)
28 #define GOTGCTL_BVALOVAL BIT(7)
29 #define GOTGCTL_BVALOEN BIT(6)
30 #define GOTGCTL_AVALOVAL BIT(5)
34 #define GOTGCTL_SESREQ BIT(1)
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/linux-6.3-rc2/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
A Dsun8i_a83t_mipi_csi2_reg.h14 #define SUN8I_A83T_MIPI_CSI2_CTRL_RESET_N BIT(31)
24 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_ECC_ERR_DBL BIT(28)
37 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_CRC_ERR_VC3 BIT(15)
70 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_3 BIT(7)
71 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_2 BIT(6)
72 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_1 BIT(5)
73 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_SOT_ERR_0 BIT(4)
128 #define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_EN BIT(31)
130 #define SUN8I_A83T_MIPI_CSI2_CFG_UNPKT_EN BIT(28)
132 #define SUN8I_A83T_MIPI_CSI2_CFG_YC_SWAB BIT(26)
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/linux-6.3-rc2/drivers/net/dsa/microchip/
A Dksz9477_reg.h43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
75 #define TRIG_TS_INT BIT(30)
130 #define SW_IBA_REQ BIT(31)
167 #define SW_RESET BIT(1)
598 #define GPIO_IN BIT(7)
599 #define GPIO_OUT BIT(6)
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/linux-6.3-rc2/drivers/comedi/drivers/
A Dni_stc.h26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
144 #define NISTC_DIO_SDIN BIT(4)
145 #define NISTC_DIO_SDOUT BIT(0)
256 #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
360 #define NISTC_RESET_G1 BIT(3)
361 #define NISTC_RESET_G0 BIT(2)
362 #define NISTC_RESET_AO BIT(1)
363 #define NISTC_RESET_AI BIT(0)
671 #define CS5529_CMD_CB BIT(7)
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/linux-6.3-rc2/include/linux/mfd/abx500/
A Dab8500-sysctrl.h83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
106 #define AB8500_STW4500CTRL1_SWOFF BIT(0)
122 #define AB8500_STW4500CTRL3_THSDENA BIT(3)
131 #define AB8500_LOWBAT_LOWBATENA BIT(0)
184 #define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
237 #define AB8500_SWATCTRL_UPDATERF BIT(0)
238 #define AB8500_SWATCTRL_SWATENABLE BIT(1)
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/linux-6.3-rc2/drivers/usb/typec/tcpm/
A Dfusb302_reg.h30 #define FUSB_REG_MEASURE_MDAC5 BIT(7)
31 #define FUSB_REG_MEASURE_MDAC4 BIT(6)
32 #define FUSB_REG_MEASURE_MDAC3 BIT(5)
33 #define FUSB_REG_MEASURE_MDAC2 BIT(4)
34 #define FUSB_REG_MEASURE_MDAC1 BIT(3)
35 #define FUSB_REG_MEASURE_MDAC0 BIT(2)
36 #define FUSB_REG_MEASURE_VBUS BIT(1)
73 #define FUSB_REG_MASK_VBUSOK BIT(7)
77 #define FUSB_REG_MASK_ALERT BIT(3)
78 #define FUSB_REG_MASK_WAKE BIT(2)
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/linux-6.3-rc2/include/linux/mfd/
A Dlp873x.h90 #define LP873X_LDO0_CTRL_LDO0_EN BIT(0)
94 #define LP873X_LDO1_CTRL_LDO1_EN BIT(0)
118 #define LP873X_GPO_CTRL_GPO2_OD BIT(6)
120 #define LP873X_GPO_CTRL_GPO2_EN BIT(4)
121 #define LP873X_GPO_CTRL_GPO_OD BIT(2)
123 #define LP873X_GPO_CTRL_GPO_EN BIT(0)
128 #define LP873X_CONFIG_CLKIN_PD BIT(3)
129 #define LP873X_CONFIG_EN_PD BIT(2)
131 #define LP873X_EN_SPREAD_SPEC BIT(0)
133 #define LP873X_PLL_CTRL_EN_PLL BIT(6)
[all …]
A Drohm-bd71815.h263 #define LDO1_EN BIT(0)
264 #define LDO2_EN BIT(1)
265 #define LDO3_EN BIT(2)
266 #define DVREF_EN BIT(3)
315 #define OUT32K_EN BIT(0)
321 #define BAT_DET BIT(5)
324 #define VBAT_OV BIT(3)
325 #define DBAT_DET BIT(0)
328 #define VBUS_DET BIT(0)
334 #define A0_ONESEC BIT(7)
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/linux-6.3-rc2/drivers/scsi/
A Dnsp32.h239 # define SD0 BIT(0)
240 # define SD1 BIT(1)
241 # define SD2 BIT(2)
242 # define SD3 BIT(3)
243 # define SD4 BIT(4)
244 # define SD5 BIT(5)
245 # define SD6 BIT(6)
246 # define SD7 BIT(7)
282 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
392 # define SCL BIT(0)
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/linux-6.3-rc2/drivers/net/ethernet/asix/
A Dax88796c_main.h121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
171 #define ISR_MDQ BIT(4)
172 #define ISR_TXT BIT(5)
175 #define ISR_LINK BIT(9)
178 #define IMR_MDQ BIT(4)
179 #define IMR_TXT BIT(5)
182 #define IMR_LINK BIT(9)
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/linux-6.3-rc2/drivers/net/ieee802154/
A Dmcr20a.h261 #define DAR_IRQSTS1_CCAIRQ BIT(3)
262 #define DAR_IRQSTS1_RXIRQ BIT(2)
263 #define DAR_IRQSTS1_TXIRQ BIT(1)
264 #define DAR_IRQSTS1_SEQIRQ BIT(0)
268 #define DAR_IRQSTS2_CCA BIT(6)
269 #define DAR_IRQSTS2_SRCADDR BIT(5)
270 #define DAR_IRQSTS2_PI BIT(4)
272 #define DAR_IRQSTS2_ASM_IRQ BIT(2)
340 #define DAR_ASM_CTRL1_CTR BIT(4)
341 #define DAR_ASM_CTRL1_CBC BIT(3)
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/linux-6.3-rc2/sound/soc/fsl/
A Dfsl_xcvr.h99 #define FSL_XCVR_EXT_CTRL_CMDC_RESET(t) (t ? BIT(29) : BIT(30))
103 #define FSL_XCVR_EXT_CTRL_DPTH_RESET(t) (t ? BIT(27) : BIT(28))
108 #define FSL_XCVR_EXT_CTRL_DMA_DIS(t) (t ? BIT(24) : BIT(25))
140 #define FSL_XCVR_IRQ_NEW_CS BIT(0)
141 #define FSL_XCVR_IRQ_NEW_UD BIT(1)
142 #define FSL_XCVR_IRQ_MUTE BIT(2)
144 #define FSL_XCVR_IRQ_ECC_ERR BIT(4)
148 #define FSL_XCVR_IRQ_HOST_OHPD BIT(8)
153 #define FSL_XCVR_IRQ_TEMP_UPD BIT(13)
171 #define FSL_XCVR_ISR_HPD_TGL BIT(15)
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