Home
last modified time | relevance | path

Searched refs:BIT_ULL (Results 1 – 25 of 436) sorted by relevance

12345678910>>...18

/linux-6.3-rc2/drivers/gpu/drm/panfrost/
A Dpanfrost_issues.h142 BIT_ULL(HW_ISSUE_9435))
145 BIT_ULL(HW_ISSUE_6367) | \
146 BIT_ULL(HW_ISSUE_6787) | \
147 BIT_ULL(HW_ISSUE_8408) | \
148 BIT_ULL(HW_ISSUE_9510) | \
158 BIT_ULL(HW_ISSUE_8186) | \
159 BIT_ULL(HW_ISSUE_8245) | \
160 BIT_ULL(HW_ISSUE_8316) | \
167 BIT_ULL(GPUCORE_1619))
182 BIT_ULL(HW_ISSUE_11035))
[all …]
A Dpanfrost_features.h30 BIT_ULL(HW_FEATURE_V4))
39 BIT_ULL(HW_FEATURE_XAFFINITY) | \
53 BIT_ULL(HW_FEATURE_XAFFINITY) | \
57 BIT_ULL(HW_FEATURE_COHERENCY_REG))
62 BIT_ULL(HW_FEATURE_XAFFINITY) | \
67 BIT_ULL(HW_FEATURE_COHERENCY_REG))
74 BIT_ULL(HW_FEATURE_XAFFINITY) | \
80 BIT_ULL(HW_FEATURE_COHERENCY_REG))
85 BIT_ULL(HW_FEATURE_XAFFINITY) | \
99 BIT_ULL(HW_FEATURE_XAFFINITY) | \
[all …]
/linux-6.3-rc2/arch/mips/include/asm/
A Dcpu.h360 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
361 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
362 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
363 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
364 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
373 #define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
374 #define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
380 #define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
401 #define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
413 BIT_ULL(54) /* CPU shares FTLB RAM with another */
[all …]
/linux-6.3-rc2/drivers/mmc/host/
A Dcavium.h134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
144 #define MIO_EMM_DMA_VAL BIT_ULL(59)
145 #define MIO_EMM_DMA_SECTOR BIT_ULL(58)
148 #define MIO_EMM_DMA_REL_WR BIT_ULL(50)
149 #define MIO_EMM_DMA_RW BIT_ULL(49)
150 #define MIO_EMM_DMA_MULTI BIT_ULL(48)
154 #define MIO_EMM_DMA_CFG_EN BIT_ULL(63)
155 #define MIO_EMM_DMA_CFG_RW BIT_ULL(62)
166 #define MIO_EMM_INT_DMA_ERR BIT_ULL(4)
[all …]
/linux-6.3-rc2/drivers/net/ethernet/cavium/thunder/
A Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
89 #define SPU_CTL_RESET BIT_ULL(15)
141 #define SMU_CTL_RX_IDLE BIT_ULL(0)
142 #define SMU_CTL_TX_IDLE BIT_ULL(1)
144 #define RX_EN BIT_ULL(0)
145 #define TX_EN BIT_ULL(1)
146 #define BCK_EN BIT_ULL(2)
[all …]
/linux-6.3-rc2/drivers/iommu/intel/
A Dcap_audit.h13 #define CAP_FL5LP_MASK BIT_ULL(60)
14 #define CAP_PI_MASK BIT_ULL(59)
15 #define CAP_FL1GP_MASK BIT_ULL(56)
16 #define CAP_RD_MASK BIT_ULL(55)
17 #define CAP_WD_MASK BIT_ULL(54)
20 #define CAP_PSI_MASK BIT_ULL(39)
23 #define CAP_ZLR_MASK BIT_ULL(22)
26 #define CAP_CM_MASK BIT_ULL(7)
27 #define CAP_PHMR_MASK BIT_ULL(6)
28 #define CAP_PLMR_MASK BIT_ULL(5)
[all …]
/linux-6.3-rc2/drivers/infiniband/hw/irdma/
A Ddefs.h465 #define IRDMA_CQ_EXTCQE BIT_ULL(50)
466 #define IRDMA_OOO_CMPL BIT_ULL(54)
467 #define IRDMA_CQ_ERROR BIT_ULL(55)
468 #define IRDMA_CQ_SQ BIT_ULL(62)
470 #define IRDMA_CQ_VALID BIT_ULL(63)
488 #define IRDMACQ_STAG BIT_ULL(53)
489 #define IRDMACQ_IPV4 BIT_ULL(53)
704 #define IRDMAQPC_IPV4 BIT_ULL(3)
707 #define IRDMAQPC_ISQP1 BIT_ULL(6)
724 #define IRDMAQPC_PMENA BIT_ULL(47)
[all …]
A Duda_d.h17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
48 #define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14)
58 #define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11)
59 #define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14)
[all …]
/linux-6.3-rc2/arch/loongarch/include/asm/
A Dcpu.h102 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
103 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
104 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
105 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
106 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
109 #define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
113 #define LOONGARCH_CPU_TLB BIT_ULL(CPU_FEATURE_TLB)
114 #define LOONGARCH_CPU_CSR BIT_ULL(CPU_FEATURE_CSR)
115 #define LOONGARCH_CPU_WATCH BIT_ULL(CPU_FEATURE_WATCH)
116 #define LOONGARCH_CPU_VINT BIT_ULL(CPU_FEATURE_VINT)
[all …]
/linux-6.3-rc2/drivers/gpu/drm/arm/display/komeda/
A Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
27 #define KOMEDA_ERR_TEMR BIT_ULL(15)
[all …]
/linux-6.3-rc2/arch/x86/include/asm/
A Dmce.h15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
33 #define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
95 #define MCI_CTL2_CMCI_EN BIT_ULL(30)
137 #define MCE_HANDLED_CEC BIT_ULL(0)
138 #define MCE_HANDLED_UC BIT_ULL(1)
139 #define MCE_HANDLED_EXTLOG BIT_ULL(2)
140 #define MCE_HANDLED_NFIT BIT_ULL(3)
141 #define MCE_HANDLED_EDAC BIT_ULL(4)
142 #define MCE_HANDLED_MCELOG BIT_ULL(5)
150 #define MCE_IN_KERNEL_RECOV BIT_ULL(6)
[all …]
A Dmsr-index.h218 #define LBR_INFO_MISPRED BIT_ULL(63)
219 #define LBR_INFO_IN_TX BIT_ULL(62)
220 #define LBR_INFO_ABORT BIT_ULL(61)
270 #define RTIT_CTL_NOTNT BIT_ULL(55)
435 #define CET_SHSTK_EN BIT_ULL(0)
436 #define CET_WRSS_EN BIT_ULL(1)
437 #define CET_ENDBR_EN BIT_ULL(2)
438 #define CET_LEG_IW_EN BIT_ULL(3)
439 #define CET_NO_TRACK_EN BIT_ULL(4)
441 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
[all …]
/linux-6.3-rc2/drivers/net/ethernet/intel/ice/
A Dice_flow.h14 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
15 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
17 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
18 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
20 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
21 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
24 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
27 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
39 (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
92 (BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI))
[all …]
/linux-6.3-rc2/drivers/firmware/efi/
A Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
33 #define INFO_VALID_IP BIT_ULL(4)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
38 #define CHECK_VALID_PCC BIT_ULL(3)
52 #define CHECK_PCC BIT_ULL(25)
53 #define CHECK_UNCORRECTED BIT_ULL(26)
54 #define CHECK_PRECISE_IP BIT_ULL(27)
56 #define CHECK_OVERFLOW BIT_ULL(29)
[all …]
/linux-6.3-rc2/drivers/net/ethernet/marvell/octeontx2/af/
A Drpm.h20 #define RPMX_RX_TS_PREPEND BIT_ULL(22)
21 #define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)
28 #define RPMX_MTI_PCS_LBK BIT_ULL(14)
63 #define RPM_TX_EN BIT_ULL(0)
64 #define RPM_RX_EN BIT_ULL(1)
79 #define RPMX_ONESTEP_ENABLE BIT_ULL(5)
80 #define RPMX_TS_BINARY_MODE BIT_ULL(11)
86 #define RPMX_RSFEC_RX_CAPTURE BIT_ULL(27)
99 #define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2)
100 #define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1)
[all …]
A Dcgx.h29 #define DATA_PKT_TX_EN BIT_ULL(53)
30 #define DATA_PKT_RX_EN BIT_ULL(54)
34 #define FW_CGX_INT BIT_ULL(1)
40 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
41 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
42 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
43 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)
44 #define CGX_DMAC_BCAST_MODE BIT_ULL(0)
46 #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
62 #define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
[all …]
/linux-6.3-rc2/include/media/
A Drc-map.h16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
25 #define RC_PROTO_BIT_NECX BIT_ULL(RC_PROTO_NECX)
26 #define RC_PROTO_BIT_NEC32 BIT_ULL(RC_PROTO_NEC32)
27 #define RC_PROTO_BIT_SANYO BIT_ULL(RC_PROTO_SANYO)
36 #define RC_PROTO_BIT_XMP BIT_ULL(RC_PROTO_XMP)
37 #define RC_PROTO_BIT_CEC BIT_ULL(RC_PROTO_CEC)
[all …]
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_gem_gtt.h41 #define PIN_NOEVICT BIT_ULL(0)
42 #define PIN_NOSEARCH BIT_ULL(1)
43 #define PIN_NONBLOCK BIT_ULL(2)
44 #define PIN_MAPPABLE BIT_ULL(3)
45 #define PIN_ZONE_4G BIT_ULL(4)
46 #define PIN_HIGH BIT_ULL(5)
47 #define PIN_OFFSET_BIAS BIT_ULL(6)
48 #define PIN_OFFSET_FIXED BIT_ULL(7)
49 #define PIN_OFFSET_GUARD BIT_ULL(8)
52 #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
[all …]
/linux-6.3-rc2/tools/arch/x86/include/asm/
A Dmsr-index.h218 #define LBR_INFO_MISPRED BIT_ULL(63)
219 #define LBR_INFO_IN_TX BIT_ULL(62)
220 #define LBR_INFO_ABORT BIT_ULL(61)
270 #define RTIT_CTL_NOTNT BIT_ULL(55)
435 #define CET_SHSTK_EN BIT_ULL(0)
436 #define CET_WRSS_EN BIT_ULL(1)
437 #define CET_ENDBR_EN BIT_ULL(2)
438 #define CET_LEG_IW_EN BIT_ULL(3)
439 #define CET_NO_TRACK_EN BIT_ULL(4)
441 #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
[all …]
/linux-6.3-rc2/drivers/net/ethernet/intel/iavf/
A Diavf.h307 #define IAVF_FLAG_AQ_ENABLE_QUEUES BIT_ULL(0)
308 #define IAVF_FLAG_AQ_DISABLE_QUEUES BIT_ULL(1)
309 #define IAVF_FLAG_AQ_ADD_MAC_FILTER BIT_ULL(2)
311 #define IAVF_FLAG_AQ_DEL_MAC_FILTER BIT_ULL(4)
314 #define IAVF_FLAG_AQ_MAP_VECTORS BIT_ULL(7)
315 #define IAVF_FLAG_AQ_HANDLE_RESET BIT_ULL(8)
317 #define IAVF_FLAG_AQ_GET_CONFIG BIT_ULL(10)
319 #define IAVF_FLAG_AQ_GET_HENA BIT_ULL(11)
320 #define IAVF_FLAG_AQ_SET_HENA BIT_ULL(12)
321 #define IAVF_FLAG_AQ_SET_RSS_KEY BIT_ULL(13)
[all …]
/linux-6.3-rc2/drivers/accel/habanalabs/gaudi2/
A Dgaudi2P.h160 #define HW_CAP_PLL BIT_ULL(0)
161 #define HW_CAP_DRAM BIT_ULL(1)
162 #define HW_CAP_PMMU BIT_ULL(2)
163 #define HW_CAP_CPU BIT_ULL(3)
164 #define HW_CAP_MSIX BIT_ULL(4)
166 #define HW_CAP_CPU_Q BIT_ULL(5)
169 #define HW_CAP_CLK_GATE BIT_ULL(6)
170 #define HW_CAP_KDMA BIT_ULL(7)
173 #define HW_CAP_DCORE0_DMMU0 BIT_ULL(9)
174 #define HW_CAP_DCORE0_DMMU1 BIT_ULL(10)
[all …]
/linux-6.3-rc2/drivers/net/ethernet/cavium/liquidio/
A Dcn66xx_regs.h367 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)
368 #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)
369 #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)
370 #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)
371 #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)
372 #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)
486 #define CN6XXX_DPI_DMA_COMMIT_MODE BIT_ULL(58)
487 #define CN6XXX_DPI_DMA_PKT_HP BIT_ULL(57)
488 #define CN6XXX_DPI_DMA_PKT_EN BIT_ULL(56)
489 #define CN6XXX_DPI_DMA_O_ES BIT_ULL(15)
[all …]
A Dcn23xx_pf_regs.h389 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
425 #define CN23XX_INTR_PO_INT BIT_ULL(63)
426 #define CN23XX_INTR_PI_INT BIT_ULL(62)
427 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)
428 #define CN23XX_INTR_RESEND BIT_ULL(60)
430 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)
451 #define CN23XX_INTR_DMA0_FORCE BIT_ULL(32)
452 #define CN23XX_INTR_DMA1_FORCE BIT_ULL(33)
454 #define CN23XX_INTR_DMA0_COUNT BIT_ULL(34)
574 #define CN23XX_DPI_DMA_COMMIT_MODE BIT_ULL(58)
[all …]
/linux-6.3-rc2/drivers/extcon/
A Dextcon-fsa9480.c128 [DEV_DEDICATED_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_DCP),
129 [DEV_USB_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
130 [DEV_CAR_KIT] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP)
132 [DEV_UART] = BIT_ULL(EXTCON_JIG),
133 [DEV_USB] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
138 [DEV_TTY] = BIT_ULL(EXTCON_JIG),
139 [DEV_PPD] = BIT_ULL(EXTCON_JACK_LINE_OUT) | BIT_ULL(EXTCON_CHG_USB_ACA),
142 [DEV_JIG_USB_OFF] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
143 [DEV_JIG_USB_ON] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
213 cables &= ~BIT_ULL(cable); in fsa9480_handle_change()
[all …]
/linux-6.3-rc2/drivers/usb/typec/tipd/
A Dtps6598x.h88 #define TPS_REG_INT_USER_VID_ALT_MODE_EXIT BIT_ULL(25+32)
90 #define TPS_REG_INT_EXIT_MODES_COMPLETE BIT_ULL(20+32)
91 #define TPS_REG_INT_DISCOVER_MODES_COMPLETE BIT_ULL(19+32)
92 #define TPS_REG_INT_VDM_MSG_SENT BIT_ULL(18+32)
93 #define TPS_REG_INT_VDM_ENTERED_MODE BIT_ULL(17+32)
94 #define TPS_REG_INT_ERROR_UNABLE_TO_SOURCE BIT_ULL(14+32)
95 #define TPS_REG_INT_SRC_TRANSITION BIT_ULL(10+32)
96 #define TPS_REG_INT_ERROR_DISCHARGE_FAILED BIT_ULL(9+32)
97 #define TPS_REG_INT_ERROR_MESSAGE_DATA BIT_ULL(7+32)
98 #define TPS_REG_INT_ERROR_PROTOCOL_ERROR BIT_ULL(6+32)
[all …]

Completed in 83 milliseconds

12345678910>>...18