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/linux-6.3-rc2/arch/sh/kernel/cpu/sh4/
A Dperf_event.c91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
106 [ C(L1I) ] = {
107 [ C(OP_READ) ] = {
121 [ C(LL) ] = {
122 [ C(OP_READ) ] = {
136 [ C(DTLB) ] = {
137 [ C(OP_READ) ] = {
151 [ C(ITLB) ] = {
166 [ C(BPU) ] = {
[all …]
/linux-6.3-rc2/arch/sh/kernel/cpu/sh4a/
A Dperf_event.c116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
131 [ C(L1I) ] = {
132 [ C(OP_READ) ] = {
146 [ C(LL) ] = {
147 [ C(OP_READ) ] = {
161 [ C(DTLB) ] = {
162 [ C(OP_READ) ] = {
176 [ C(ITLB) ] = {
191 [ C(BPU) ] = {
[all …]
/linux-6.3-rc2/arch/x86/events/zhaoxin/
A Dcore.c51 [C(L1D)] = {
65 [C(L1I)] = {
79 [C(LL)] = {
93 [C(DTLB)] = {
107 [C(ITLB)] = {
121 [C(BPU)] = {
135 [C(NODE)] = {
155 [C(L1D)] = {
169 [C(L1I)] = {
183 [C(LL)] = {
[all …]
/linux-6.3-rc2/arch/powerpc/perf/
A Dpower10-pmu.c358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
373 [C(L1I)] = {
387 [C(LL)] = {
429 [C(BPU)] = {
459 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
460 [C(L1D)] = {
474 [C(L1I)] = {
488 [C(LL)] = {
530 [C(BPU)] = {
[all …]
A Dgeneric-compat-pmu.c185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
200 [ C(L1I) ] = {
201 [ C(OP_READ) ] = {
214 [ C(LL) ] = {
228 [ C(DTLB) ] = {
242 [ C(ITLB) ] = {
256 [ C(BPU) ] = {
270 [ C(NODE) ] = {
[all …]
A Dpower8-pmu.c266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
281 [ C(L1I) ] = {
282 [ C(OP_READ) ] = {
295 [ C(LL) ] = {
309 [ C(DTLB) ] = {
323 [ C(ITLB) ] = {
337 [ C(BPU) ] = {
351 [ C(NODE) ] = {
[all …]
A Dpower9-pmu.c337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
352 [ C(L1I) ] = {
353 [ C(OP_READ) ] = {
366 [ C(LL) ] = {
380 [ C(DTLB) ] = {
394 [ C(ITLB) ] = {
408 [ C(BPU) ] = {
422 [ C(NODE) ] = {
[all …]
A De6500-pmu.c35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
53 [C(LL)] = {
55 [C(OP_READ)] = { 0, 0 },
56 [C(OP_WRITE)] = { 0, 0 },
65 [C(DTLB)] = {
71 [C(BPU)] = {
[all …]
A De500-pmu.c34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
56 [C(OP_READ)] = { 0, 0 },
57 [C(OP_WRITE)] = { 0, 0 },
67 [C(OP_READ)] = { 26, 66 },
68 [C(OP_WRITE)] = { -1, -1 },
[all …]
/linux-6.3-rc2/arch/arm/kernel/
A Dperf_event_v7.c192 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
193 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
195 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
196 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
236 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
239 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
518 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
524 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
526 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
527 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
[all …]
/linux-6.3-rc2/arch/x86/events/intel/
A Dp6.c28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
33 [ C(OP_WRITE) ] = {
42 [ C(L1I ) ] = {
43 [ C(OP_READ) ] = {
56 [ C(LL ) ] = {
57 [ C(OP_READ) ] = {
70 [ C(DTLB) ] = {
71 [ C(OP_READ) ] = {
84 [ C(ITLB) ] = {
[all …]
A Dknc.c26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
36 [ C(OP_WRITE) ] = {
45 [ C(L1I ) ] = {
46 [ C(OP_READ) ] = {
59 [ C(LL ) ] = {
60 [ C(OP_READ) ] = {
73 [ C(DTLB) ] = {
74 [ C(OP_READ) ] = {
89 [ C(ITLB) ] = {
[all …]
A Dcore.c1855 [C(LL)] = {
1917 [C(LL)] = {
1971 [C(LL)] = {
6130 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6157 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6334 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
6336 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
6338 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
6340 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
6456 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
[all …]
/linux-6.3-rc2/drivers/perf/
A Driscv_pmu_sbi.c115 [C(L1D)] = {
118 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
120 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
124 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
126 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
138 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
139 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
155 [C(LL)] = {
158 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
160 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
[all …]
/linux-6.3-rc2/tools/testing/selftests/bpf/progs/
A Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
A Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
A Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
A Dcore_kern.c85 #define C do { \ in balancer_ingress() macro
99 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/linux-6.3-rc2/arch/sparc/kernel/
A Dperf_event.c221 [C(L1D)] = {
235 [C(L1I)] = {
249 [C(LL)] = {
291 [C(BPU)] = {
359 [C(L1D)] = {
373 [C(L1I)] = {
387 [C(LL)] = {
429 [C(BPU)] = {
494 [C(L1D)] = {
522 [C(LL)] = {
[all …]
/linux-6.3-rc2/arch/mips/kernel/
A Dperf_event_mipsxx.c1010 [C(L1D)] = {
1026 [C(L1I)] = {
1043 [C(LL)] = {
1073 [C(BPU)] = {
1091 [C(L1D)] = {
1107 [C(L1I)] = {
1124 [C(LL)] = {
1149 [C(BPU)] = {
1284 [C(LL)] = {
1346 [C(LL)] = {
[all …]
/linux-6.3-rc2/arch/x86/events/amd/
A Dcore.c31 [ C(L1D) ] = {
45 [ C(L1I ) ] = {
59 [ C(LL ) ] = {
73 [ C(DTLB) ] = {
135 [C(L1D)] = {
149 [C(L1I)] = {
163 [C(LL)] = {
177 [C(DTLB)] = {
191 [C(ITLB)] = {
205 [C(BPU)] = {
[all …]
/linux-6.3-rc2/lib/zstd/common/
A Dcpu.h98 C(sse3, 0)
103 C(vmx, 5)
104 C(smx, 6)
105 C(eist, 7)
106 C(tm2, 8)
109 C(fma, 12)
114 C(dca, 18)
121 C(aes, 25)
124 C(avx, 28)
127 #undef C
[all …]
/linux-6.3-rc2/kernel/trace/
A Dtrace_probe.h402 C(NO_REGULAR_FILE, "Not a regular file"), \
409 C(MAXACT_TOO_BIG, "Maxactive is too big"), \
421 C(BAD_STACK_NUM, "Invalid stack number"), \
424 C(BAD_REG_NAME, "Invalid register name"), \
426 C(BAD_IMM, "Invalid immediate value"), \
437 C(ARRAY_NO_CLOSE, "Array is not closed"), \
439 C(BAD_ARRAY_NUM, "Invalid array size"), \
441 C(BAD_TYPE, "Unknown type is specified"), \
444 C(BAD_BITFIELD, "Invalid bitfield"), \
461 #undef C
[all …]
/linux-6.3-rc2/arch/arm64/kernel/
A Dperf_event.c60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
75 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
[all …]
/linux-6.3-rc2/lib/crypto/
A Dsha1.c61 TEMP = E; E = D; D = C; C = B; B = A; A = TEMP; } while (0)
63 #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
64 #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
65 #define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) argument
66 #define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D,… argument
67 #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) argument
89 __u32 A, B, C, D, E; in sha1_transform() local
94 C = digest[2]; in sha1_transform()
100 T_0_15(i, A, B, C, D, E); in sha1_transform()
104 T_16_19(i, A, B, C, D, E); in sha1_transform()
[all …]

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