1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) ST-Ericsson SA 2012
4  *
5  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
6  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>
7  *         for ST-Ericsson.
8  */
9 
10 #ifndef UX500_msp_dai_H
11 #define UX500_msp_dai_H
12 
13 #include <linux/types.h>
14 #include <linux/spinlock.h>
15 
16 #include "ux500_msp_i2s.h"
17 
18 #define UX500_NBR_OF_DAI	4
19 
20 #define UX500_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |	\
21 			SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
22 
23 #define UX500_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
24 
25 #define FRAME_PER_SINGLE_SLOT_8_KHZ		31
26 #define FRAME_PER_SINGLE_SLOT_16_KHZ	124
27 #define FRAME_PER_SINGLE_SLOT_44_1_KHZ	63
28 #define FRAME_PER_SINGLE_SLOT_48_KHZ	49
29 #define FRAME_PER_2_SLOTS				31
30 #define FRAME_PER_8_SLOTS				138
31 #define FRAME_PER_16_SLOTS				277
32 
33 #define UX500_MSP_INTERNAL_CLOCK_FREQ  40000000
34 #define UX500_MSP1_INTERNAL_CLOCK_FREQ UX500_MSP_INTERNAL_CLOCK_FREQ
35 
36 #define UX500_MSP_MIN_CHANNELS		1
37 #define UX500_MSP_MAX_CHANNELS		8
38 
39 #define PLAYBACK_CONFIGURED		1
40 #define CAPTURE_CONFIGURED		2
41 
42 enum ux500_msp_clock_id {
43 	UX500_MSP_MASTER_CLOCK,
44 };
45 
46 struct ux500_msp_i2s_drvdata {
47 	struct ux500_msp *msp;
48 	struct regulator *reg_vape;
49 	unsigned int fmt;
50 	unsigned int tx_mask;
51 	unsigned int rx_mask;
52 	int slots;
53 	int slot_width;
54 
55 	/* Clocks */
56 	unsigned int master_clk;
57 	struct clk *clk;
58 	struct clk *pclk;
59 
60 	/* Regulators */
61 	int vape_opp_constraint;
62 };
63 
64 int ux500_msp_dai_set_data_delay(struct snd_soc_dai *dai, int delay);
65 
66 #endif
67