Searched refs:CGU_CLK_DIV (Results 1 – 10 of 10) sorted by relevance
| /linux-6.3-rc2/drivers/clk/ingenic/ |
| A D | jz4740-cgu.c | 95 "pll half", CGU_CLK_DIV,
104 "cclk", CGU_CLK_DIV,
118 "hclk", CGU_CLK_DIV,
127 "pclk", CGU_CLK_DIV,
136 "mclk", CGU_CLK_DIV,
150 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
160 "lcd_pclk", CGU_CLK_DIV,
166 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
174 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
182 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | jz4770-cgu.c | 151 "cclk", CGU_CLK_DIV,
164 "h0clk", CGU_CLK_DIV,
172 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
181 "h2clk", CGU_CLK_DIV,
189 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
198 "pclk", CGU_CLK_DIV,
230 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
237 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
244 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
275 "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
[all …]
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| A D | jz4760-cgu.c | 143 "cclk", CGU_CLK_DIV,
156 "hclk", CGU_CLK_DIV,
164 "sclk", CGU_CLK_DIV,
172 "h2clk", CGU_CLK_DIV,
180 "mclk", CGU_CLK_DIV,
193 "pclk", CGU_CLK_DIV,
204 "pll0_half", CGU_CLK_DIV,
265 "i2s", CGU_CLK_DIV | CGU_CLK_MUX,
282 "mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
288 "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
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| A D | jz4755-cgu.c | 77 "pll half", CGU_CLK_DIV,
86 "ext half", CGU_CLK_DIV,
95 "cclk", CGU_CLK_DIV,
104 "hclk", CGU_CLK_DIV,
113 "pclk", CGU_CLK_DIV,
122 "mclk", CGU_CLK_DIV,
131 "h1clk", CGU_CLK_DIV,
148 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
155 "mmc", CGU_CLK_DIV,
161 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
[all …]
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| A D | jz4725b-cgu.c | 80 "pll half", CGU_CLK_DIV,
89 "cclk", CGU_CLK_DIV,
103 "hclk", CGU_CLK_DIV,
112 "pclk", CGU_CLK_DIV,
121 "mclk", CGU_CLK_DIV,
135 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
145 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
152 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
159 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
167 "mmc_mux", CGU_CLK_DIV,
[all …]
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| A D | jz4780-cgu.c | 343 "cpu", CGU_CLK_DIV,
354 "l2cache", CGU_CLK_DIV,
365 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
380 "ahb2", CGU_CLK_DIV,
386 "pclk", CGU_CLK_DIV,
392 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
413 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
448 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
455 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
462 "msc2", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | x1830-cgu.c | 227 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
235 "l2cache", CGU_CLK_DIV,
246 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
259 "ahb2", CGU_CLK_DIV,
265 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
272 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
285 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
294 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
310 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
317 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | x1000-cgu.c | 286 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
298 "l2cache", CGU_CLK_DIV,
309 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
322 "ahb2", CGU_CLK_DIV,
328 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
335 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
348 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
387 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
401 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
408 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| A D | cgu.c | 415 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
502 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
534 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
692 if (caps & CGU_CLK_DIV) { in ingenic_register_clock()
693 caps &= ~CGU_CLK_DIV; in ingenic_register_clock()
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| A D | cgu.h | 167 CGU_CLK_DIV = BIT(5), enumerator
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