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Searched refs:CLASS2_ENABLE_MAILBOX_INTR (Results 1 – 4 of 4) sorted by relevance

/linux-6.3-rc2/arch/powerpc/platforms/cell/spufs/
A Dhw_ops.c65 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); in spu_hw_mbox_stat_poll()
96 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); in spu_hw_ibox_read()
A Dbacking_ops.c98 CLASS2_ENABLE_MAILBOX_INTR; in spu_backing_mbox_stat_poll()
132 ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR; in spu_backing_ibox_read()
A Dswitch.c1682 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); in check_ppuint_mb_stat()
/linux-6.3-rc2/arch/powerpc/include/asm/
A Dspu.h476 #define CLASS2_ENABLE_MAILBOX_INTR 0x1L macro

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