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Searched refs:CLKID_VCLK_DIV2 (Results 1 – 8 of 8) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Daxg-clkc.h88 #define CLKID_VCLK_DIV2 123 macro
A Dg12a-clkc.h114 #define CLKID_VCLK_DIV2 149 macro
A Dgxbb-clkc.h135 #define CLKID_VCLK_DIV2 186 macro
/linux-6.3-rc2/drivers/clk/meson/
A Dmeson8b.h128 #define CLKID_VCLK_DIV2 142 macro
A Dmeson8b.c2916 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3124 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3343 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
A Dgxbb.c2911 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
3122 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
A Dg12a.c4399 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4628 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4892 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
A Daxg.c2017 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,

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