Searched refs:CLK_FIN_PLL (Results 1 – 20 of 20) sorted by relevance
/linux-6.3-rc2/Documentation/devicetree/bindings/timer/ |
A D | samsung,exynos4210-mct.yaml | 165 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 185 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 206 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 226 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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/linux-6.3-rc2/include/dt-bindings/clock/ |
A D | exynos5410.h | 13 #define CLK_FIN_PLL 1 macro
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A D | exynos5250.h | 13 #define CLK_FIN_PLL 1 macro
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A D | exynos4.h | 15 #define CLK_FIN_PLL 3 macro
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A D | exynos5420.h | 13 #define CLK_FIN_PLL 1 macro
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A D | exynos3250.h | 26 #define CLK_FIN_PLL 2 macro
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/linux-6.3-rc2/arch/arm/boot/dts/ |
A D | exynos3250.dtsi | 355 clocks = <&cmu CLK_FIN_PLL>; 406 assigned-clock-parents = <&cmu CLK_FIN_PLL>, 407 <&cmu CLK_FIN_PLL>; 459 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
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A D | exynos5250.dtsi | 241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 296 clocks = <&clock CLK_FIN_PLL>; 658 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 689 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
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A D | exynos5420.dtsi | 298 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 939 clocks = <&clock CLK_FIN_PLL>; 1293 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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A D | exynos4210.dtsi | 286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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A D | exynos5250-snow-common.dtsi | 672 assigned-clock-parents = <&clock CLK_FIN_PLL>;
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A D | exynos4412.dtsi | 443 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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A D | exynos4.dtsi | 70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
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A D | exynos5420-peach-pit.dts | 942 assigned-clock-parents = <&clock CLK_FIN_PLL>;
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A D | exynos5800-peach-pi.dts | 924 assigned-clock-parents = <&clock CLK_FIN_PLL>;
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/linux-6.3-rc2/Documentation/devicetree/bindings/soc/samsung/ |
A D | exynos-pmu.yaml | 165 clocks = <&clock CLK_FIN_PLL>;
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/linux-6.3-rc2/drivers/clk/samsung/ |
A D | clk-exynos5250.c | 225 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 809 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init()
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A D | clk-exynos4.c | 1054 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll() 1267 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init() 1281 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
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A D | clk-exynos5420.c | 445 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 1597 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5x_clk_init()
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A D | clk-exynos3250.c | 234 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
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