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Searched refs:CLK_FIN_PLL (Results 1 – 20 of 20) sorted by relevance

/linux-6.3-rc2/Documentation/devicetree/bindings/timer/
A Dsamsung,exynos4210-mct.yaml165 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
185 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
206 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
226 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
/linux-6.3-rc2/include/dt-bindings/clock/
A Dexynos5410.h13 #define CLK_FIN_PLL 1 macro
A Dexynos5250.h13 #define CLK_FIN_PLL 1 macro
A Dexynos4.h15 #define CLK_FIN_PLL 3 macro
A Dexynos5420.h13 #define CLK_FIN_PLL 1 macro
A Dexynos3250.h26 #define CLK_FIN_PLL 2 macro
/linux-6.3-rc2/arch/arm/boot/dts/
A Dexynos3250.dtsi355 clocks = <&cmu CLK_FIN_PLL>;
406 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
407 <&cmu CLK_FIN_PLL>;
459 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
A Dexynos5250.dtsi241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
296 clocks = <&clock CLK_FIN_PLL>;
658 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
689 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
A Dexynos5420.dtsi298 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
939 clocks = <&clock CLK_FIN_PLL>;
1293 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos4210.dtsi286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos5250-snow-common.dtsi672 assigned-clock-parents = <&clock CLK_FIN_PLL>;
A Dexynos4412.dtsi443 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos4.dtsi70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
A Dexynos5420-peach-pit.dts942 assigned-clock-parents = <&clock CLK_FIN_PLL>;
A Dexynos5800-peach-pi.dts924 assigned-clock-parents = <&clock CLK_FIN_PLL>;
/linux-6.3-rc2/Documentation/devicetree/bindings/soc/samsung/
A Dexynos-pmu.yaml165 clocks = <&clock CLK_FIN_PLL>;
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-exynos5250.c225 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
809 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init()
A Dclk-exynos4.c1054 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll()
1267 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
1281 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
A Dclk-exynos5420.c445 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
1597 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5x_clk_init()
A Dclk-exynos3250.c234 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),

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