Home
last modified time | relevance | path

Searched refs:CLK_IS_CRITICAL (Results 1 – 25 of 162) sorted by relevance

1234567

/linux-6.3-rc2/drivers/clk/st/
A Dclk-flexgen.c307 { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
317 { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
318 { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
336 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
343 { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
353 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
356 { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
381 { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
388 { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
398 { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
[all …]
/linux-6.3-rc2/drivers/clk/rockchip/
A Dclk-rk3588.c807 CLK_IS_CRITICAL,
819 CLK_IS_CRITICAL,
1312 CLK_IS_CRITICAL,
1316 CLK_IS_CRITICAL,
1320 CLK_IS_CRITICAL,
1324 CLK_IS_CRITICAL,
1332 CLK_IS_CRITICAL,
1336 CLK_IS_CRITICAL,
2196 GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
2292 CLK_IS_CRITICAL,
[all …]
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8186-infra_ao.c74 "infra_ao_scp_core", "top_scp", 4, CLK_IS_CRITICAL),
77 "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
106 "infra_ao_dvfsrc", "top_dvfsrc", 7, CLK_IS_CRITICAL),
118 "infra_ao_dapc", "top_axi", 20, CLK_IS_CRITICAL),
145 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM, "infra_ao_sspm", "top_sspm", 15, CLK_IS_CRITICAL),
167 CLK_IS_CRITICAL),
169 CLK_IS_CRITICAL),
177 "infra_ao_sej_f13m", "clk26m", 15, CLK_IS_CRITICAL),
180 "infra_ao_aes_top0_bclk", "top_axi", 16, CLK_IS_CRITICAL),
A Dclk-mt7986-topckgen.c208 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
213 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
217 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
221 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
247 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
266 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
A Dclk-mt8195-infra_ao.c86 GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
124 CLK_IS_CRITICAL),
145 CLK_IS_CRITICAL),
147 CLK_IS_CRITICAL),
172 CLK_IS_CRITICAL),
179 CLK_IS_CRITICAL),
181 CLK_IS_CRITICAL),
A Dclk-mt8195-topckgen.c865 axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL),
867 spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL),
869 scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, CLK_IS_CRITICAL),
871 bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL),
954 pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL),
1023 mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, CLK_IS_CRITICAL),
1033 dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, CLK_IS_CRITICAL),
1144 ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, CLK_IS_CRITICAL),
1146 ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, CLK_IS_CRITICAL),
1148 srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL),
[all …]
A Dclk-mt7981-topckgen.c322 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
326 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
331 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
335 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
339 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
A Dclk-mt8186-topckgen.c507 CLK_IS_CRITICAL),
510 CLK_IS_CRITICAL),
562 CLK_IS_CRITICAL),
573 CLK_IS_CRITICAL),
576 CLK_IS_CRITICAL),
630 CLK_IS_CRITICAL),
A Dclk-mt6795-topckgen.c453 0x40, 0, 3, 7, CLK_IS_CRITICAL),
455 0x40, 8, 1, 15, CLK_IS_CRITICAL),
457 0x40, 16, 1, 23, CLK_IS_CRITICAL),
493 0xa0, 16, 3, 23, CLK_IS_CRITICAL),
A Dclk-mt8173-topckgen.c533 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
536 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
582 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
604 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
A Dclk-mt8192.c553 CLK_IS_CRITICAL),
556 CLK_IS_CRITICAL),
561 CLK_IS_CRITICAL),
846 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL),
909 CLK_IS_CRITICAL),
919 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL),
920 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL),
/linux-6.3-rc2/drivers/clk/imx/
A Dclk-imx93.c56 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
57 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
58 { IMX93_CLK_A55, "a55_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
59 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
60 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
61 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
62 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
116 { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL},
158 { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL },
246 { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL},
A Dclk-imx5.c147 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2_flags("ahb_max", "ahb", MXC_CCM_CCGR0, 28, CLK_IS_CRITICAL); in mx5_clocks_common_init()
148 …k[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", MXC_CCM_CCGR0, 24, CLK_IS_CRITICAL); in mx5_clocks_common_init()
149 …k[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", MXC_CCM_CCGR0, 26, CLK_IS_CRITICAL); in mx5_clocks_common_init()
150 clk[IMX5_CLK_TMAX1] = imx_clk_gate2_flags("tmax1", "ahb", MXC_CCM_CCGR1, 0, CLK_IS_CRITICAL); in mx5_clocks_common_init()
151 clk[IMX5_CLK_TMAX2] = imx_clk_gate2_flags("tmax2", "ahb", MXC_CCM_CCGR1, 2, CLK_IS_CRITICAL); in mx5_clocks_common_init()
152 clk[IMX5_CLK_TMAX3] = imx_clk_gate2_flags("tmax3", "ahb", MXC_CCM_CCGR1, 4, CLK_IS_CRITICAL); in mx5_clocks_common_init()
153 clk[IMX5_CLK_SPBA] = imx_clk_gate2_flags("spba", "ipg", MXC_CCM_CCGR5, 0, CLK_IS_CRITICAL); in mx5_clocks_common_init()
218 …EMI_FAST_GATE] = imx_clk_gate2_flags("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14, CLK_IS_CRITICAL); in mx5_clocks_common_init()
233 …IMX5_CLK_GPC_DVFS] = imx_clk_gate2_flags("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24, CLK_IS_CRITICAL); in mx5_clocks_common_init()
419 …K_MIPI_ESC_GATE] = imx_clk_gate2_flags("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10, CLK_IS_CRITICAL); in mx51_clocks_init()
[all …]
A Dclk-imx6sx.c370 …6SX_CLK_AIPS_TZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); in imx6sx_clocks_init()
371 …6SX_CLK_AIPS_TZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); in imx6sx_clocks_init()
384 …SX_CLK_AIPS_TZ3] = imx_clk_hw_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL); in imx6sx_clocks_init()
397 …X6SX_CLK_WAKEUP] = imx_clk_hw_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL); in imx6sx_clocks_init()
411 …X6SX_CLK_IPMUX1] = imx_clk_hw_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL); in imx6sx_clocks_init()
412 …X6SX_CLK_IPMUX2] = imx_clk_hw_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL); in imx6sx_clocks_init()
413 …X6SX_CLK_IPMUX3] = imx_clk_hw_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL); in imx6sx_clocks_init()
429 …CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); in imx6sx_clocks_init()
430 …CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg", base + 0x74, 26, CLK_IS_CRITICAL); in imx6sx_clocks_init()
437 …X_CLK_PER2_MAIN] = imx_clk_hw_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_CRITICAL); in imx6sx_clocks_init()
[all …]
A Dclk-imx6sll.c161 …LK_USBPHY1_GATE] = imx_clk_hw_gate_flags("usbphy1_gate", "dummy", base + 0x10, 6, CLK_IS_CRITICAL); in imx6sll_clocks_init()
162 …LK_USBPHY2_GATE] = imx_clk_hw_gate_flags("usbphy2_gate", "dummy", base + 0x20, 6, CLK_IS_CRITICAL); in imx6sll_clocks_init()
260 …[IMX6SLL_CLK_AIPSTZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); in imx6sll_clocks_init()
261 …[IMX6SLL_CLK_AIPSTZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); in imx6sll_clocks_init()
302 …C_P0_FAST] = imx_clk_hw_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); in imx6sll_clocks_init()
303 …K_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); in imx6sll_clocks_init()
304 …K_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg", base + 0x74, 26, CLK_IS_CRITICAL); in imx6sll_clocks_init()
305 …[IMX6SLL_CLK_OCRAM] = imx_clk_hw_gate_flags("ocram", "ahb", base + 0x74, 28, CLK_IS_CRITICAL); in imx6sll_clocks_init()
314 hws[IMX6SLL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); in imx6sll_clocks_init()
A Dclk-imx7ulp.c115 … imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30,… in imx7ulp_clk_scg1_init()
118 …_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx7ulp_clk_scg1_init()
119 …_divider_flags("nic1_clk", "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx7ulp_clk_scg1_init()
120 …vider_flags("nic1_bus_clk", "nic0_clk", base + 0x40, 4, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx7ulp_clk_scg1_init()
204 …_CLK_MMDC] = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, in imx7ulp_clk_pcc3_init()
A Dclk-imx8ulp.c197 …_hw_divider_flags("a35_div", "a35_sel", base + 0x14, 21, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx8ulp_clk_cgc1_init()
200 …ider_flags("nic_ad_divplat", "nic_sel", base + 0x34, 21, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx8ulp_clk_cgc1_init()
201 …gs("nic_per_divplat", "nic_ad_divplat", base + 0x34, 14, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx8ulp_clk_cgc1_init()
202 …gs("xbar_ad_divplat", "nic_ad_divplat", base + 0x38, 14, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx8ulp_clk_cgc1_init()
203 …r_flags("xbar_divbus", "nic_ad_divplat", base + 0x38, 7, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx8ulp_clk_cgc1_init()
204 …_flags("xbar_ad_slow", "nic_ad_divplat", base + 0x38, 0, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); in imx8ulp_clk_cgc1_init()
259 …CLK_DDR_DIV] = imx_clk_hw_divider_flags("ddr_div", "ddr_sel", base + 0x40, 21, 6, CLK_IS_CRITICAL); in imx8ulp_clk_cgc2_init()
261 …I_DIV] = imx_clk_hw_divider_flags("lpav_axi_div", "lpav_sel", base + 0x3c, 21, 6, CLK_IS_CRITICAL); in imx8ulp_clk_cgc2_init()
262 …V] = imx_clk_hw_divider_flags("lpav_ahb_div", "lpav_axi_div", base + 0x3c, 14, 6, CLK_IS_CRITICAL); in imx8ulp_clk_cgc2_init()
263 …IV] = imx_clk_hw_divider_flags("lpav_bus_div", "lpav_axi_div", base + 0x3c, 7, 6, CLK_IS_CRITICAL); in imx8ulp_clk_cgc2_init()
/linux-6.3-rc2/drivers/clk/bcm/
A Dclk-bcm63xx-gate.c130 .flags = CLK_IS_CRITICAL,
143 .flags = CLK_IS_CRITICAL,
174 .flags = CLK_IS_CRITICAL,
178 .flags = CLK_IS_CRITICAL,
185 .flags = CLK_IS_CRITICAL,
222 .flags = CLK_IS_CRITICAL,
301 .flags = CLK_IS_CRITICAL,
425 .flags = CLK_IS_CRITICAL,
/linux-6.3-rc2/drivers/clk/starfive/
A Dclk-starfive-jh7100.c92 JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
93 JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
94 JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
95 JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
96 JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
97 JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
129 JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
132 JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
133 JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
138 JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
[all …]
/linux-6.3-rc2/drivers/clk/baikal-t1/
A Dclk-ccu-pll.c67 CLK_IS_CRITICAL, CCU_PLL_BASIC),
69 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
71 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
73 CLK_IS_CRITICAL, CCU_PLL_BASIC),
75 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0)
/linux-6.3-rc2/drivers/clk/microchip/
A Dclk-mpfs.c297 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
302 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
314 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
319 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
320 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL),
321 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL),
322 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL),
323 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL),
324 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL),
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-exynos7885.c631 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
634 CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
640 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0),
642 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0),
644 CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
647 CLK_IS_CRITICAL, 0),
650 CLK_IS_CRITICAL, 0),
652 CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
655 CLK_IS_CRITICAL, 0),
A Dclk-exynos5420.c943 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
947 GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
949 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
953 GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
959 GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
963 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
965 GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
967 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
969 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
1166 CLK_IS_CRITICAL, 0),
[all …]
/linux-6.3-rc2/drivers/clk/tegra/
A Dclk-tegra-super-gen4.c118 CLK_IS_CRITICAL, in tegra_sclk_init()
131 CLK_IS_CRITICAL, in tegra_sclk_init()
145 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, in tegra_sclk_init()
160 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
/linux-6.3-rc2/drivers/clk/at91/
A Dsam9x60.c85 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
145 { .n = "mpddr_clk", .id = 49, .flags = CLK_IS_CRITICAL },
244 CLK_IS_CRITICAL | CLK_SET_RATE_GATE); in sam9x60_pmc_setup()
255 CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); in sam9x60_pmc_setup()

Completed in 56 milliseconds

1234567