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Searched refs:CLK_MCT (Results 1 – 17 of 17) sorted by relevance

/linux-6.3-rc2/Documentation/devicetree/bindings/timer/
A Dsamsung,exynos4210-mct.yaml165 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
185 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
206 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
226 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
/linux-6.3-rc2/include/dt-bindings/clock/
A Dexynos5410.h50 #define CLK_MCT 315 macro
A Dexynos5250.h139 #define CLK_MCT 335 macro
A Dexynos4.h182 #define CLK_MCT 344 macro
A Dexynos5420.h108 #define CLK_MCT 315 macro
A Dexynos3250.h153 #define CLK_MCT 147 macro
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-exynos5410.c167 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
A Dclk-exynos4.c945 GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
985 GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
A Dclk-exynos5250.c625 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
A Dclk-exynos3250.c478 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
A Dclk-exynos5420.c1123 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
/linux-6.3-rc2/arch/arm/boot/dts/
A Dexynos5410.dtsi319 clocks = <&fin_pll>, <&clock CLK_MCT>;
A Dexynos4210.dtsi286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos4412.dtsi443 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos3250.dtsi459 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
A Dexynos5250.dtsi251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
A Dexynos5420.dtsi1293 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;

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