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Searched refs:CLK_MM_DISP_OVL0_2L (Results 1 – 15 of 15) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt6765-mm.c40 GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),
A Dclk-mt8183-mm.c57 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
A Dclk-mt8186-mm.c37 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "top_disp", 4),
A Dclk-mt6779-mm.c57 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
A Dclk-mt6797-mm.c62 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
A Dclk-mt8192-mm.c47 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt6797-clk.h232 #define CLK_MM_DISP_OVL0_2L 18 macro
A Dmt6765-clk.h259 #define CLK_MM_DISP_OVL0_2L 8 macro
A Dmt6779-clk.h361 #define CLK_MM_DISP_OVL0_2L 21 macro
A Dmt8183-clk.h329 #define CLK_MM_DISP_OVL0_2L 20 macro
A Dmt8186-clk.h305 #define CLK_MM_DISP_OVL0_2L 4 macro
A Dmt8192-clk.h428 #define CLK_MM_DISP_OVL0_2L 4 macro
/linux-6.3-rc2/Documentation/devicetree/bindings/display/mediatek/
A Dmediatek,ovl-2l.yaml88 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
/linux-6.3-rc2/arch/arm64/boot/dts/mediatek/
A Dmt8192.dtsi1342 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
A Dmt8183.dtsi1853 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;

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