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Searched refs:CLK_MM_DISP_PWM0_MM (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt2712-mm.c93 GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
/linux-6.3-rc2/include/dt-bindings/clock/
A Dmt2712-clk.h331 #define CLK_MM_DISP_PWM0_MM 30 macro

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